Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::crc5_cg

Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_crc5	3	0	3	100.00	100	1	1	0
cp_dir	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_crc5_X_dir	6	0	6	100.00	100	1	1	0

Summary for Variable cp_crc5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_crc5

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	7592	1			T43	2		T4	15		T159	8
leading_zero	5226	1			T29	13		T32	1		T166	13
trailing_zero	6338	1			T32	2		T35	2		T17	2

---

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116191

1

T2

1

T3

1

T28

1

auto[1]

70465

1

T29

5

T42

1

T43

10

---

Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for cr_crc5_X_dir

Bins

cp_crc5	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	auto[0]	5007	1			T43	1		T4	7		T159	4
all_ones	auto[1]	2585	1			T43	1		T4	8		T159	4
leading_zero	auto[0]	2880	1			T29	8		T166	6		T67	14
leading_zero	auto[1]	2346	1			T29	5		T32	1		T166	7
trailing_zero	auto[0]	4073	1			T32	1		T35	1		T17	1
trailing_zero	auto[1]	2265	1			T32	1		T35	1		T17	1