Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116033

1

T2

1

T3

1

T28

1

auto[1]

47036

1

T29

5

T32

9

T33

1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28745	1			T37	1		T39	1		T83	1
max_len_m1	911	1			T171	1		T66	2		T4	1
max_len_m2	872	1			T37	1		T66	1		T5	2
max_len_m3	868	1			T49	1		T52	1		T66	1
five	1236	1			T66	1		T54	1		T108	4
four	1245	1			T66	1		T4	3		T108	1
three	853	1			T35	2		T66	1		T4	2
one	921	1			T39	2		T66	2		T159	1
zero	12328	1			T2	1		T29	5		T32	5

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23184	1			T37	1		T39	1		T83	1
max_len	auto[1]	5561	1			T118	1		T92	48		T119	1
max_len_m1	auto[0]	621	1			T171	1		T66	2		T4	1
max_len_m1	auto[1]	290	1			T5	1		T165	1		T67	1
max_len_m2	auto[0]	595	1			T37	1		T66	1		T5	1
max_len_m2	auto[1]	277	1			T5	1		T119	1		T165	1
max_len_m3	auto[0]	606	1			T52	1		T66	1		T6	1
max_len_m3	auto[1]	262	1			T49	1		T6	1		T119	2
five	auto[0]	662	1			T66	1		T54	1		T108	2
five	auto[1]	574	1			T108	2		T158	1		T166	1
four	auto[0]	645	1			T66	1		T4	2		T108	1
four	auto[1]	600	1			T4	1		T67	3		T102	5
three	auto[0]	405	1			T35	1		T66	1		T4	2
three	auto[1]	448	1			T35	1		T67	2		T102	13
one	auto[0]	418	1			T39	2		T66	2		T159	1
one	auto[1]	503	1			T67	6		T102	12		T581	1
zero	auto[0]	586	1			T2	1		T35	1		T566	1
zero	auto[1]	11742	1			T29	5		T32	5		T35	1