Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140829

1

T3

2

T28

2

T29

16

auto[1]

80715

1

T29

10

T32

15

T33

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	17602	1			T32	2		T35	4		T400	2
endpoints[0x1]	19240	1			T32	3		T35	4		T17	4
endpoints[0x2]	17274	1			T32	8		T35	4		T24	2
endpoints[0x3]	19732	1			T28	2		T32	4		T35	4
endpoints[0x4]	20636	1			T35	4		T36	2		T39	21
endpoints[0x5]	16246	1			T35	4		T37	21		T161	4
endpoints[0x6]	15772	1			T30	15		T32	3		T35	4
endpoints[0x7]	17643	1			T32	2		T33	4		T35	4
endpoints[0x8]	16449	1			T32	2		T35	4		T118	4
endpoints[0x9]	21502	1			T3	2		T32	2		T35	4
endpoints[0xa]	19002	1			T32	7		T35	4		T38	14
endpoints[0xb]	20446	1			T29	26		T34	4		T35	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1575	1			T32	3		T37	2		T39	2
ack	107055	1			T3	1		T28	1		T29	13
data1	52154	1			T29	3		T30	1		T32	10
data0	60689	1			T3	1		T28	1		T29	10

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	100	1			T116	10		T117	3		T183	5
nak	auto[0]	endpoints[0x1]	152	1			T54	1		T68	5		T58	1
nak	auto[0]	endpoints[0x2]	80	1			T126	1		T116	6		T582	1
nak	auto[0]	endpoints[0x3]	110	1			T72	1		T543	1		T127	1
nak	auto[0]	endpoints[0x4]	155	1			T39	2		T583	1		T183	5
nak	auto[0]	endpoints[0x5]	146	1			T37	2		T573	12		T138	1
nak	auto[0]	endpoints[0x6]	56	1			T141	1		T142	1		T584	1
nak	auto[0]	endpoints[0x7]	141	1			T182	14		T338	1		T585	9
nak	auto[0]	endpoints[0x8]	107	1			T71	2		T117	6		T302	1
nak	auto[0]	endpoints[0x9]	147	1			T285	1		T544	1		T150	1
nak	auto[0]	endpoints[0xa]	97	1			T117	3		T586	1		T153	1
nak	auto[0]	endpoints[0xb]	106	1			T68	9		T587	1		T458	9
nak	auto[1]	endpoints[0x0]	17	1			T108	1		T581	1		T588	1
nak	auto[1]	endpoints[0x1]	12	1			T581	1		T589	2		T590	2
nak	auto[1]	endpoints[0x2]	19	1			T32	1		T108	1		T114	1
nak	auto[1]	endpoints[0x3]	15	1			T32	1		T581	1		T590	1
nak	auto[1]	endpoints[0x4]	23	1			T108	1		T574	1		T591	1
nak	auto[1]	endpoints[0x5]	11	1			T589	1		T590	1		T592	1
nak	auto[1]	endpoints[0x6]	13	1			T581	2		T588	1		T589	1
nak	auto[1]	endpoints[0x7]	19	1			T108	1		T589	2		T574	1
nak	auto[1]	endpoints[0x8]	9	1			T581	1		T593	1		T588	1
nak	auto[1]	endpoints[0x9]	13	1			T32	1		T594	2		T595	1
nak	auto[1]	endpoints[0xa]	14	1			T108	1		T581	1		T589	1
nak	auto[1]	endpoints[0xb]	13	1			T108	1		T574	1		T596	2
ack	auto[0]	endpoints[0x0]	5259	1			T35	1		T400	1		T8	1
ack	auto[0]	endpoints[0x1]	5688	1			T35	1		T17	1		T54	7
ack	auto[0]	endpoints[0x2]	5193	1			T32	3		T35	1		T24	1
ack	auto[0]	endpoints[0x3]	5930	1			T28	1		T32	1		T35	1
ack	auto[0]	endpoints[0x4]	6692	1			T35	1		T36	1		T39	8
ack	auto[0]	endpoints[0x5]	4593	1			T35	1		T37	8		T161	1
ack	auto[0]	endpoints[0x6]	4509	1			T30	7		T32	1		T35	1
ack	auto[0]	endpoints[0x7]	5281	1			T32	1		T33	1		T35	1
ack	auto[0]	endpoints[0x8]	4658	1			T32	1		T35	1		T118	1
ack	auto[0]	endpoints[0x9]	6766	1			T3	1		T35	1		T4	7
ack	auto[0]	endpoints[0xa]	6250	1			T32	2		T35	1		T38	7
ack	auto[0]	endpoints[0xb]	6476	1			T29	8		T34	1		T35	1
ack	auto[1]	endpoints[0x0]	3251	1			T32	1		T35	1		T8	1
ack	auto[1]	endpoints[0x1]	3614	1			T32	1		T35	1		T17	1
ack	auto[1]	endpoints[0x2]	3114	1			T35	1		T108	1		T158	1
ack	auto[1]	endpoints[0x3]	3601	1			T35	1		T160	1		T4	7
ack	auto[1]	endpoints[0x4]	3229	1			T35	1		T5	33		T6	8
ack	auto[1]	endpoints[0x5]	3215	1			T35	1		T161	1		T49	1
ack	auto[1]	endpoints[0x6]	3092	1			T35	1		T162	1		T163	1
ack	auto[1]	endpoints[0x7]	3184	1			T33	1		T35	1		T4	7
ack	auto[1]	endpoints[0x8]	3287	1			T35	1		T118	1		T60	10
ack	auto[1]	endpoints[0x9]	3674	1			T35	1		T4	7		T108	2
ack	auto[1]	endpoints[0xa]	3022	1			T32	1		T35	1		T108	1
ack	auto[1]	endpoints[0xb]	3477	1			T29	5		T35	1		T51	1
data1	auto[0]	endpoints[0x0]	2368	1			T6	4		T119	21		T67	8
data1	auto[0]	endpoints[0x1]	2542	1			T54	4		T165	13		T166	2
data1	auto[0]	endpoints[0x2]	2325	1			T32	2		T159	1		T67	9
data1	auto[0]	endpoints[0x3]	2597	1			T72	1		T160	1		T4	2
data1	auto[0]	endpoints[0x4]	3060	1			T39	5		T5	11		T6	4
data1	auto[0]	endpoints[0x5]	2089	1			T37	5		T49	1		T249	5
data1	auto[0]	endpoints[0x6]	1970	1			T30	1		T162	1		T4	2
data1	auto[0]	endpoints[0x7]	2394	1			T32	1		T4	3		T110	1
data1	auto[0]	endpoints[0x8]	2027	1			T32	1		T71	5		T4	2
data1	auto[0]	endpoints[0x9]	3069	1			T4	3		T166	3		T67	3
data1	auto[0]	endpoints[0xa]	2853	1			T108	1		T159	1		T67	14
data1	auto[0]	endpoints[0xb]	2920	1			T29	1		T51	1		T52	1
data1	auto[1]	endpoints[0x0]	1764	1			T32	1		T6	4		T108	1
data1	auto[1]	endpoints[0x1]	2007	1			T32	2		T165	28		T166	4
data1	auto[1]	endpoints[0x2]	1737	1			T108	1		T159	2		T67	6
data1	auto[1]	endpoints[0x3]	2030	1			T32	1		T160	1		T4	5
data1	auto[1]	endpoints[0x4]	1778	1			T5	22		T6	4		T108	1
data1	auto[1]	endpoints[0x5]	1740	1			T49	1		T109	1		T107	9
data1	auto[1]	endpoints[0x6]	1672	1			T32	1		T162	1		T4	5
data1	auto[1]	endpoints[0x7]	1728	1			T4	4		T110	1		T108	3
data1	auto[1]	endpoints[0x8]	1851	1			T60	8		T4	4		T110	2
data1	auto[1]	endpoints[0x9]	2031	1			T4	4		T108	1		T166	3
data1	auto[1]	endpoints[0xa]	1672	1			T32	1		T159	2		T67	7
data1	auto[1]	endpoints[0xb]	1930	1			T29	2		T51	1		T52	1
data0	auto[0]	endpoints[0x0]	3281	1			T35	1		T400	1		T8	1
data0	auto[0]	endpoints[0x1]	3534	1			T35	1		T17	1		T54	4
data0	auto[0]	endpoints[0x2]	3337	1			T32	1		T35	1		T24	1
data0	auto[0]	endpoints[0x3]	3749	1			T28	1		T32	1		T35	1
data0	auto[0]	endpoints[0x4]	4162	1			T35	1		T36	1		T39	6
data0	auto[0]	endpoints[0x5]	2887	1			T35	1		T37	6		T161	1
data0	auto[0]	endpoints[0x6]	2963	1			T30	7		T32	1		T35	1
data0	auto[0]	endpoints[0x7]	3336	1			T33	1		T35	1		T82	1
data0	auto[0]	endpoints[0x8]	2997	1			T35	1		T118	1		T71	6
data0	auto[0]	endpoints[0x9]	4082	1			T3	1		T35	1		T200	1
data0	auto[0]	endpoints[0xa]	3673	1			T32	2		T35	1		T38	7
data0	auto[0]	endpoints[0xb]	3901	1			T29	7		T34	1		T35	1
data0	auto[1]	endpoints[0x0]	1558	1			T35	1		T8	1		T6	4
data0	auto[1]	endpoints[0x1]	1685	1			T35	1		T17	1		T158	1
data0	auto[1]	endpoints[0x2]	1463	1			T32	1		T35	1		T108	1
data0	auto[1]	endpoints[0x3]	1692	1			T35	1		T4	2		T6	4
data0	auto[1]	endpoints[0x4]	1532	1			T35	1		T5	11		T6	4
data0	auto[1]	endpoints[0x5]	1558	1			T35	1		T161	1		T109	5
data0	auto[1]	endpoints[0x6]	1487	1			T35	1		T163	1		T4	2
data0	auto[1]	endpoints[0x7]	1550	1			T33	1		T35	1		T4	3
data0	auto[1]	endpoints[0x8]	1509	1			T35	1		T118	1		T60	7
data0	auto[1]	endpoints[0x9]	1717	1			T32	1		T35	1		T4	3
data0	auto[1]	endpoints[0xa]	1416	1			T32	1		T35	1		T108	2
data0	auto[1]	endpoints[0xb]	1620	1			T29	3		T34	1		T35	1