Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8910 1 T43 9 T243 4 T115 2
auto[1] 55778 1 T29 5 T43 1 T31 1


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57082 1 T29 5 T43 10 T31 1
auto[1] 7606 1 T36 1 T92 51 T115 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57830 1 T29 5 T43 9 T32 9
auto[1] 6858 1 T43 1 T31 1 T243 5


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4722 1 T43 4 T243 4 T115 1
pkt_types[PidTypeInToken] 59966 1 T29 5 T43 6 T31 1


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1369 1 T43 3 T243 3 T159 1
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 829 1 T68 4 T432 2 T116 24
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 85 1 T115 1 T159 1 T202 1
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 17 1 T457 1 T474 1 T453 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1483 1 T159 3 T68 11 T116 30
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 826 1 T43 1 T243 1 T68 13
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 93 1 T597 5 T434 2 T404 4
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 20 1 T430 1 T444 1 T474 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3994 1 T43 6 T243 1 T68 52
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2528 1 T115 1 T68 22 T432 7
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 35 1 T598 1 T499 1 T524 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 53 1 T462 1 T474 1 T464 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 43523 1 T29 5 T32 9 T33 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2530 1 T31 1 T243 4 T106 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7248 1 T36 1 T92 51 T105 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 55 1 T524 1 T441 1 T464 2

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