Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.92	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	2	52	96.30

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	2	52	96.30	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19835	1			T30	1		T54	1		T4	61
solo	78405	1			T2	1		T29	8		T42	3
empty	5218	1			T3	1		T28	1		T30	7

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19865	1			T21	2		T4	61		T5	33
solo	36463	1			T3	1		T28	1		T42	1
empty	47160	1			T2	1		T29	8		T42	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

78112

1

T2

1

T29

8

T42

2

setup

25534

1

T3

1

T28

1

T42

1

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	53	1			T302	1		T198	1		T195	1
solo	178	1			T30	1		T37	1		T39	1
empty	85554	1			T2	1		T3	1		T28	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	2	52	96.30	2

Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[empty]	[solo]	[empty]	[setup]	0	1	1
[empty]	[empty]	[solo]	[out]	0	1	1

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	2	1			T302	1		T303	1		-	-
full	full	full	setup	3	1			T304	1		T305	1		T306	1
full	full	solo	out	1	1			T307	1		-	-		-	-
full	full	solo	setup	4	1			T308	1		T309	1		T310	1
full	full	empty	out	15231	1			T4	45		T5	19		T6	25
full	full	empty	setup	4528	1			T4	16		T5	14		T6	7
full	solo	full	out	2	1			T311	1		T312	1		-	-
full	solo	full	setup	7	1			T313	1		T314	1		T315	1
full	solo	solo	out	3	1			T316	1		T317	1		T318	1
full	solo	solo	setup	6	1			T319	1		T320	1		T321	1
full	solo	empty	out	3	1			T322	1		T323	1		T324	1
full	solo	empty	setup	3	1			T325	1		T326	1		T327	1
full	empty	full	out	1	1			T328	1		-	-		-	-
full	empty	full	setup	3	1			T329	1		T330	1		T331	1
full	empty	solo	out	4	1			T332	1		T333	1		T334	1
full	empty	solo	setup	12	1			T335	1		T336	1		T337	1
full	empty	empty	out	2	1			T338	1		T339	1		-	-
full	empty	empty	setup	9	1			T57	1		T340	1		T341	1
solo	full	full	out	3	1			T342	1		T343	1		T344	1
solo	full	full	setup	2	1			T195	1		T345	1		-	-
solo	full	solo	out	6	1			T346	1		T347	1		T348	1
solo	full	solo	setup	1	1			T349	1		-	-		-	-
solo	full	empty	out	8	1			T54	1		T58	1		T350	1
solo	full	empty	setup	2	1			T351	1		T352	1		-	-
solo	solo	full	out	6	1			T353	1		T354	1		T355	1
solo	solo	full	setup	6	1			T356	1		T357	1		T358	1
solo	solo	solo	out	9	1			T54	1		T58	1		T350	1
solo	solo	solo	setup	9	1			T54	1		T55	1		T58	1
solo	solo	empty	out	9167	1			T43	4		T171	1		T243	7
solo	solo	empty	setup	9156	1			T42	1		T43	7		T171	1
solo	empty	full	out	2	1			T359	1		T360	1		-	-
solo	empty	full	setup	3	1			T361	1		T362	1		T363	1
solo	empty	solo	out	5	1			T364	1		T365	1		T366	1
solo	empty	solo	setup	73	1			T168	1		T302	1		T367	1
solo	empty	empty	out	3	1			T368	1		T369	1		T370	1
solo	empty	empty	setup	2161	1			T3	1		T28	1		T30	1
empty	full	full	out	1	1			T371	1		-	-		-	-
empty	full	full	setup	4	1			T372	1		T373	1		T374	1
empty	full	solo	out	4	1			T30	1		T375	1		T376	1
empty	full	solo	setup	3	1			T377	1		T378	1		T379	1
empty	full	empty	out	11	1			T380	1		T381	1		T382	1
empty	full	empty	setup	2	1			T383	1		T384	1		-	-
empty	solo	full	out	2	1			T198	1		T385	1		-	-
empty	solo	full	setup	2	1			T386	1		T387	1		-	-
empty	solo	solo	out	4	1			T388	1		T389	1		T390	1
empty	solo	solo	setup	3	1			T391	1		T392	1		T393	1
empty	solo	empty	out	44808	1			T2	1		T29	8		T42	2
empty	empty	full	out	2	1			T394	1		T395	1		-	-
empty	empty	full	setup	2	1			T196	1		T396	1		-	-
empty	empty	solo	setup	5	1			T194	1		T397	1		T398	1
empty	empty	empty	out	261	1			T37	1		T39	1		T71	1
empty	empty	empty	setup	164	1			T200	1		T201	1		T399	1