Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	169871	1			T1	7		T2	3		T3	4
all_pins[1]	169871	1			T1	7		T2	3		T3	4
all_pins[2]	169871	1			T1	7		T2	3		T3	4
all_pins[3]	169871	1			T1	7		T2	3		T3	4
all_pins[4]	169871	1			T1	7		T2	3		T3	4
all_pins[5]	169871	1			T1	7		T2	3		T3	4
all_pins[6]	169871	1			T1	7		T2	3		T3	4
all_pins[7]	169871	1			T1	7		T2	3		T3	4
all_pins[8]	169871	1			T1	7		T2	3		T3	4
all_pins[9]	169871	1			T1	7		T2	3		T3	4
all_pins[10]	169871	1			T1	7		T2	3		T3	4
all_pins[11]	169871	1			T1	7		T2	3		T3	4
all_pins[12]	169871	1			T1	7		T2	3		T3	4
all_pins[13]	169871	1			T1	7		T2	3		T3	4
all_pins[14]	169871	1			T1	7		T2	3		T3	4
all_pins[15]	169871	1			T1	7		T2	3		T3	4
all_pins[16]	169871	1			T1	7		T2	3		T3	4
all_pins[17]	169871	1			T1	7		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5433608	1			T1	222		T2	95		T3	128
values[0x1]	2264	1			T1	2		T2	1		T28	1
transitions[0x0=>0x1]	1986	1			T1	2		T2	1		T28	1
transitions[0x1=>0x0]	1986	1			T1	2		T2	1		T28	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	169751	1			T1	7		T2	3		T3	4
all_pins[0]	values[0x1]	120	1			T400	1		T401	1		T402	1
all_pins[0]	transitions[0x0=>0x1]	105	1			T400	1		T401	1		T402	1
all_pins[0]	transitions[0x1=>0x0]	856	1			T33	1		T35	12		T17	1
all_pins[1]	values[0x0]	169000	1			T1	7		T2	3		T3	4
all_pins[1]	values[0x1]	871	1			T33	1		T35	12		T17	1
all_pins[1]	transitions[0x0=>0x1]	856	1			T33	1		T35	12		T17	1
all_pins[1]	transitions[0x1=>0x0]	127	1			T41	1		T64	1		T65	1
all_pins[2]	values[0x0]	169729	1			T1	7		T2	3		T3	4
all_pins[2]	values[0x1]	142	1			T41	1		T64	1		T65	1
all_pins[2]	transitions[0x0=>0x1]	120	1			T41	1		T64	1		T65	1
all_pins[2]	transitions[0x1=>0x0]	36	1			T66	1		T223	1		T224	2
all_pins[3]	values[0x0]	169813	1			T1	7		T2	3		T3	4
all_pins[3]	values[0x1]	58	1			T66	1		T223	1		T224	2
all_pins[3]	transitions[0x0=>0x1]	45	1			T66	1		T223	1		T224	2
all_pins[3]	transitions[0x1=>0x0]	51	1			T50	1		T221	6		T223	1
all_pins[4]	values[0x0]	169807	1			T1	7		T2	3		T3	4
all_pins[4]	values[0x1]	64	1			T50	1		T221	6		T223	1
all_pins[4]	transitions[0x0=>0x1]	52	1			T50	1		T221	6		T224	1
all_pins[4]	transitions[0x1=>0x0]	61	1			T221	1		T223	2		T224	1
all_pins[5]	values[0x0]	169798	1			T1	7		T2	3		T3	4
all_pins[5]	values[0x1]	73	1			T221	1		T223	3		T224	1
all_pins[5]	transitions[0x0=>0x1]	51	1			T221	1		T223	2		T224	1
all_pins[5]	transitions[0x1=>0x0]	96	1			T20	1		T69	1		T70	1
all_pins[6]	values[0x0]	169753	1			T1	7		T2	3		T3	4
all_pins[6]	values[0x1]	118	1			T20	1		T69	1		T70	1
all_pins[6]	transitions[0x0=>0x1]	106	1			T20	1		T69	1		T70	1
all_pins[6]	transitions[0x1=>0x0]	50	1			T53	1		T221	1		T223	2
all_pins[7]	values[0x0]	169809	1			T1	7		T2	3		T3	4
all_pins[7]	values[0x1]	62	1			T53	1		T221	1		T223	2
all_pins[7]	transitions[0x0=>0x1]	45	1			T53	1		T221	1		T223	1
all_pins[7]	transitions[0x1=>0x0]	70	1			T21	1		T56	1		T57	1
all_pins[8]	values[0x0]	169784	1			T1	7		T2	3		T3	4
all_pins[8]	values[0x1]	87	1			T21	1		T56	1		T57	1
all_pins[8]	transitions[0x0=>0x1]	72	1			T21	1		T56	1		T57	1
all_pins[8]	transitions[0x1=>0x0]	62	1			T1	2		T62	2		T63	2
all_pins[9]	values[0x0]	169794	1			T1	5		T2	3		T3	4
all_pins[9]	values[0x1]	77	1			T1	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	56	1			T1	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	44	1			T223	2		T224	2		T300	2
all_pins[10]	values[0x0]	169806	1			T1	7		T2	3		T3	4
all_pins[10]	values[0x1]	65	1			T223	2		T224	2		T300	2
all_pins[10]	transitions[0x0=>0x1]	49	1			T223	1		T300	2		T294	4
all_pins[10]	transitions[0x1=>0x0]	83	1			T19	1		T73	1		T74	1
all_pins[11]	values[0x0]	169772	1			T1	7		T2	3		T3	4
all_pins[11]	values[0x1]	99	1			T19	1		T73	1		T74	1
all_pins[11]	transitions[0x0=>0x1]	89	1			T19	1		T73	1		T74	1
all_pins[11]	transitions[0x1=>0x0]	49	1			T23	1		T75	1		T77	1
all_pins[12]	values[0x0]	169812	1			T1	7		T2	3		T3	4
all_pins[12]	values[0x1]	59	1			T23	1		T75	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	43	1			T23	1		T75	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	89	1			T2	1		T80	1		T81	1
all_pins[13]	values[0x0]	169766	1			T1	7		T2	2		T3	4
all_pins[13]	values[0x1]	105	1			T2	1		T80	1		T81	1
all_pins[13]	transitions[0x0=>0x1]	90	1			T2	1		T80	1		T81	1
all_pins[13]	transitions[0x1=>0x0]	42	1			T221	1		T223	3		T224	1
all_pins[14]	values[0x0]	169814	1			T1	7		T2	3		T3	4
all_pins[14]	values[0x1]	57	1			T221	1		T223	3		T224	1
all_pins[14]	transitions[0x0=>0x1]	36	1			T221	1		T223	3		T292	2
all_pins[14]	transitions[0x1=>0x0]	40	1			T221	2		T223	1		T291	3
all_pins[15]	values[0x0]	169810	1			T1	7		T2	3		T3	4
all_pins[15]	values[0x1]	61	1			T221	2		T223	1		T224	1
all_pins[15]	transitions[0x0=>0x1]	42	1			T221	2		T291	3		T300	1
all_pins[15]	transitions[0x1=>0x0]	65	1			T37	4		T39	4		T71	4
all_pins[16]	values[0x0]	169787	1			T1	7		T2	3		T3	4
all_pins[16]	values[0x1]	84	1			T37	4		T39	4		T71	4
all_pins[16]	transitions[0x0=>0x1]	67	1			T37	4		T39	4		T71	4
all_pins[16]	transitions[0x1=>0x0]	45	1			T28	1		T24	1		T59	1
all_pins[17]	values[0x0]	169809	1			T1	7		T2	3		T3	4
all_pins[17]	values[0x1]	62	1			T28	1		T24	1		T59	1
all_pins[17]	transitions[0x0=>0x1]	62	1			T28	1		T24	1		T59	1