Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4818	1			T42	1		T4	5		T68	51
invalid_ep[0xd]	4816	1			T4	10		T115	1		T68	54
invalid_ep[0xe]	4913	1			T4	6		T68	55		T116	102
invalid_ep[0xf]	4936	1			T42	1		T4	5		T115	2
endpoints[0x0]	13552	1			T32	1		T35	2		T400	1
endpoints[0x1]	14792	1			T32	2		T35	2		T17	2
endpoints[0x2]	13213	1			T32	4		T35	2		T24	1
endpoints[0x3]	14069	1			T28	1		T42	1		T43	19
endpoints[0x4]	14818	1			T42	1		T43	3		T35	2
endpoints[0x5]	12626	1			T43	2		T35	2		T37	11
endpoints[0x6]	12849	1			T2	1		T30	8		T43	4
endpoints[0x7]	13152	1			T31	1		T32	1		T33	2
endpoints[0x8]	13059	1			T43	2		T32	1		T35	2
endpoints[0x9]	15327	1			T3	1		T43	1		T32	1
endpoints[0xa]	14175	1			T42	1		T32	4		T35	2
endpoints[0xb]	15541	1			T29	13		T34	2		T35	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	25534	1			T3	1		T28	1		T42	1
pkt_types[PidTypeOutToken]	78112	1			T2	1		T29	8		T42	2
pkt_types[PidTypeInToken]	64275	1			T29	5		T42	1		T43	6

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1057	1			T68	15		T116	20		T117	13
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1106	1			T115	1		T68	11		T116	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1098	1			T68	25		T116	27		T117	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1134	1			T68	19		T116	25		T117	19
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1720	1			T54	1		T119	24		T159	2
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1865	1			T243	1		T165	22		T166	3
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1748	1			T24	1		T159	2		T68	17
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1976	1			T28	1		T43	1		T160	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1788	1			T43	1		T5	14		T166	4
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1592	1			T43	1		T49	1		T243	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1668	1			T30	7		T43	1		T85	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1627	1			T4	2		T110	1		T68	12
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1816	1			T43	2		T4	4		T110	2
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1755	1			T3	1		T43	1		T200	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1722	1			T42	1		T38	7		T171	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1862	1			T51	1		T52	1		T22	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1679	1			T4	5		T68	9		T116	25
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1583	1			T4	10		T68	16		T116	18
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1581	1			T4	6		T68	6		T116	27
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1592	1			T42	1		T4	5		T68	13
pkt_types[PidTypeOutToken]	endpoints[0x0]	5685	1			T35	1		T400	1		T8	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	6001	1			T35	1		T17	1		T66	140
pkt_types[PidTypeOutToken]	endpoints[0x2]	5627	1			T32	3		T35	1		T158	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5998	1			T43	4		T32	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	7072	1			T42	1		T43	2		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	5092	1			T35	1		T37	11		T161	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	4998	1			T2	1		T30	1		T32	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5773	1			T32	1		T33	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5056	1			T32	1		T35	1		T118	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	7039	1			T35	1		T4	6		T158	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	6561	1			T32	2		T35	1		T171	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6775	1			T29	8		T34	1		T35	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1077	1			T42	1		T68	14		T116	21
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1038	1			T68	15		T116	16		T117	16
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1103	1			T68	10		T116	22		T117	11
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1091	1			T115	2		T68	11		T462	1
pkt_types[PidTypeInToken]	endpoints[0x0]	4941	1			T32	1		T35	1		T8	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5684	1			T32	2		T35	1		T17	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4610	1			T32	1		T35	1		T108	2
pkt_types[PidTypeInToken]	endpoints[0x3]	4881	1			T43	6		T32	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4718	1			T35	1		T36	1		T5	34
pkt_types[PidTypeInToken]	endpoints[0x5]	4792	1			T35	1		T161	1		T49	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4987	1			T32	1		T35	1		T162	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4582	1			T31	1		T33	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4987	1			T35	1		T118	1		T60	15
pkt_types[PidTypeInToken]	endpoints[0x9]	5351	1			T32	1		T35	1		T4	8
pkt_types[PidTypeInToken]	endpoints[0xa]	4702	1			T32	2		T35	1		T92	51
pkt_types[PidTypeInToken]	endpoints[0xb]	5731	1			T29	5		T34	1		T35	1