Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T221	7		T223	7		T224	7
all_values[1]	281	1			T221	7		T223	7		T224	7
all_values[2]	281	1			T221	7		T223	7		T224	7
all_values[3]	281	1			T221	7		T223	7		T224	7
all_values[4]	281	1			T221	7		T223	7		T224	7
all_values[5]	281	1			T221	7		T223	7		T224	7
all_values[6]	281	1			T221	7		T223	7		T224	7
all_values[7]	281	1			T221	7		T223	7		T224	7
all_values[8]	281	1			T221	7		T223	7		T224	7
all_values[9]	281	1			T221	7		T223	7		T224	7
all_values[10]	281	1			T221	7		T223	7		T224	7
all_values[11]	281	1			T221	7		T223	7		T224	7
all_values[12]	281	1			T221	7		T223	7		T224	7
all_values[13]	281	1			T221	7		T223	7		T224	7
all_values[14]	281	1			T221	7		T223	7		T224	7
all_values[15]	281	1			T221	7		T223	7		T224	7
all_values[16]	281	1			T221	7		T223	7		T224	7
all_values[17]	281	1			T221	7		T223	7		T224	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6733

1

T221

157

T223

158

T224

172

auto[1]

2259

1

T221

67

T223

66

T224

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6165

1

T221

152

T223

154

T224

149

auto[1]

2827

1

T221

72

T223

70

T224

75

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5271

1

T221

133

T223

130

T224

129

auto[1]

3721

1

T221

91

T223

94

T224

95

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	90	1			T221	2		T223	1		T224	2
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T221	4		T223	2		T291	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1			T223	1		T224	3		T291	2
all_values[0]	auto[1]	auto[1]	auto[1]	55	1			T221	1		T223	3		T224	2
all_values[1]	auto[0]	auto[0]	auto[0]	94	1			T221	1		T223	2		T224	1
all_values[1]	auto[0]	auto[1]	auto[0]	73	1			T221	1		T223	2		T291	1
all_values[1]	auto[1]	auto[0]	auto[1]	67	1			T221	1		T223	2		T224	4
all_values[1]	auto[1]	auto[1]	auto[1]	47	1			T221	4		T223	1		T224	2
all_values[2]	auto[0]	auto[0]	auto[0]	33	1			T221	1		T292	1		T293	2
all_values[2]	auto[0]	auto[0]	auto[1]	45	1			T221	1		T223	2		T224	2
all_values[2]	auto[0]	auto[1]	auto[0]	28	1			T294	1		T295	3		T296	3
all_values[2]	auto[0]	auto[1]	auto[1]	41	1			T221	1		T223	3		T224	2
all_values[2]	auto[1]	auto[0]	auto[1]	68	1			T221	2		T223	2		T224	2
all_values[2]	auto[1]	auto[1]	auto[1]	66	1			T221	2		T224	1		T291	1
all_values[3]	auto[0]	auto[0]	auto[0]	71	1			T221	2		T223	3		T224	3
all_values[3]	auto[0]	auto[0]	auto[1]	25	1			T224	1		T297	1		T292	1
all_values[3]	auto[0]	auto[1]	auto[0]	50	1			T221	2		T223	3		T291	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1			T294	4		T298	1		T299	1
all_values[3]	auto[1]	auto[0]	auto[1]	53	1			T221	1		T224	2		T297	1
all_values[3]	auto[1]	auto[1]	auto[1]	57	1			T221	2		T223	1		T224	1
all_values[4]	auto[0]	auto[0]	auto[0]	74	1			T223	3		T224	2		T297	2
all_values[4]	auto[0]	auto[0]	auto[1]	27	1			T221	1		T224	1		T300	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1			T223	2		T224	1		T291	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1			T221	3		T291	1		T292	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1			T223	1		T224	1		T291	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T221	3		T223	1		T224	2
all_values[5]	auto[0]	auto[0]	auto[0]	51	1			T221	1		T224	3		T291	1
all_values[5]	auto[0]	auto[0]	auto[1]	26	1			T221	2		T223	1		T297	1
all_values[5]	auto[0]	auto[1]	auto[0]	52	1			T221	1		T224	2		T291	1
all_values[5]	auto[0]	auto[1]	auto[1]	34	1			T221	1		T223	1		T300	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1			T221	1		T223	3		T291	2
all_values[5]	auto[1]	auto[1]	auto[1]	52	1			T221	1		T223	2		T224	2
all_values[6]	auto[0]	auto[0]	auto[0]	46	1			T221	3		T223	1		T291	2
all_values[6]	auto[0]	auto[0]	auto[1]	30	1			T221	2		T224	3		T298	1
all_values[6]	auto[0]	auto[1]	auto[0]	53	1			T223	4		T291	1		T292	5
all_values[6]	auto[0]	auto[1]	auto[1]	25	1			T297	2		T300	3		T294	1
all_values[6]	auto[1]	auto[0]	auto[1]	74	1			T221	2		T223	1		T224	3
all_values[6]	auto[1]	auto[1]	auto[1]	53	1			T223	1		T224	1		T297	1
all_values[7]	auto[0]	auto[0]	auto[0]	92	1			T221	4		T223	1		T224	1
all_values[7]	auto[0]	auto[1]	auto[0]	65	1			T223	1		T224	2		T291	1
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T221	1		T223	4		T224	1
all_values[7]	auto[1]	auto[1]	auto[1]	55	1			T221	2		T223	1		T224	3
all_values[8]	auto[0]	auto[0]	auto[0]	99	1			T221	1		T223	3		T224	1
all_values[8]	auto[0]	auto[1]	auto[0]	69	1			T221	5		T224	3		T297	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1			T221	1		T223	2		T291	2
all_values[8]	auto[1]	auto[1]	auto[1]	45	1			T223	2		T224	3		T297	2
all_values[9]	auto[0]	auto[0]	auto[0]	60	1			T221	1		T223	3		T224	2
all_values[9]	auto[0]	auto[0]	auto[1]	29	1			T221	1		T223	1		T224	1
all_values[9]	auto[0]	auto[1]	auto[0]	46	1			T221	1		T223	1		T224	1
all_values[9]	auto[0]	auto[1]	auto[1]	27	1			T221	1		T224	1		T297	2
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T221	1		T223	2		T224	2
all_values[9]	auto[1]	auto[1]	auto[1]	45	1			T221	2		T297	1		T292	2
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T221	2		T224	3		T291	2
all_values[10]	auto[0]	auto[0]	auto[1]	32	1			T223	3		T297	2		T300	2
all_values[10]	auto[0]	auto[1]	auto[0]	66	1			T221	3		T223	1		T224	1
all_values[10]	auto[0]	auto[1]	auto[1]	28	1			T224	1		T294	3		T301	1
all_values[10]	auto[1]	auto[0]	auto[1]	66	1			T223	1		T224	1		T297	2
all_values[10]	auto[1]	auto[1]	auto[1]	46	1			T221	2		T223	2		T224	1
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T221	1		T223	1		T224	1
all_values[11]	auto[0]	auto[0]	auto[1]	28	1			T291	1		T300	1		T301	1
all_values[11]	auto[0]	auto[1]	auto[0]	64	1			T221	3		T223	4		T224	1
all_values[11]	auto[0]	auto[1]	auto[1]	19	1			T224	1		T300	1		T294	1
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T221	2		T224	1		T291	1
all_values[11]	auto[1]	auto[1]	auto[1]	39	1			T221	1		T223	2		T224	3
all_values[12]	auto[0]	auto[0]	auto[0]	76	1			T221	2		T224	4		T291	2
all_values[12]	auto[0]	auto[0]	auto[1]	26	1			T221	1		T224	1		T300	1
all_values[12]	auto[0]	auto[1]	auto[0]	48	1			T221	1		T224	1		T291	1
all_values[12]	auto[0]	auto[1]	auto[1]	24	1			T223	3		T298	2		T301	1
all_values[12]	auto[1]	auto[0]	auto[1]	65	1			T221	2		T223	3		T291	1
all_values[12]	auto[1]	auto[1]	auto[1]	42	1			T221	1		T223	1		T224	1
all_values[13]	auto[0]	auto[0]	auto[0]	72	1			T223	1		T224	3		T291	2
all_values[13]	auto[0]	auto[0]	auto[1]	26	1			T221	2		T223	2		T224	1
all_values[13]	auto[0]	auto[1]	auto[0]	56	1			T221	2		T223	3		T224	1
all_values[13]	auto[0]	auto[1]	auto[1]	24	1			T297	1		T300	1		T298	1
all_values[13]	auto[1]	auto[0]	auto[1]	54	1			T221	1		T223	1		T224	1
all_values[13]	auto[1]	auto[1]	auto[1]	49	1			T221	2		T224	1		T291	1
all_values[14]	auto[0]	auto[0]	auto[0]	60	1			T221	1		T224	1		T291	3
all_values[14]	auto[0]	auto[0]	auto[1]	27	1			T300	2		T294	1		T298	1
all_values[14]	auto[0]	auto[1]	auto[0]	54	1			T221	2		T223	3		T224	2
all_values[14]	auto[0]	auto[1]	auto[1]	23	1			T221	1		T223	1		T300	1
all_values[14]	auto[1]	auto[0]	auto[1]	74	1			T221	2		T223	1		T224	3
all_values[14]	auto[1]	auto[1]	auto[1]	43	1			T221	1		T223	2		T224	1
all_values[15]	auto[0]	auto[0]	auto[0]	68	1			T221	1		T223	1		T291	1
all_values[15]	auto[0]	auto[0]	auto[1]	33	1			T221	1		T223	2		T224	1
all_values[15]	auto[0]	auto[1]	auto[0]	52	1			T221	1		T223	3		T224	2
all_values[15]	auto[0]	auto[1]	auto[1]	26	1			T221	1		T291	1		T292	1
all_values[15]	auto[1]	auto[0]	auto[1]	53	1			T224	2		T292	2		T300	1
all_values[15]	auto[1]	auto[1]	auto[1]	49	1			T221	3		T223	1		T224	2
all_values[16]	auto[0]	auto[0]	auto[0]	49	1			T223	2		T224	1		T292	2
all_values[16]	auto[0]	auto[0]	auto[1]	28	1			T221	1		T224	2		T297	2
all_values[16]	auto[0]	auto[1]	auto[0]	50	1			T221	2		T223	2		T291	2
all_values[16]	auto[0]	auto[1]	auto[1]	26	1			T224	1		T292	1		T300	1
all_values[16]	auto[1]	auto[0]	auto[1]	66	1			T221	2		T224	3		T291	1
all_values[16]	auto[1]	auto[1]	auto[1]	62	1			T221	2		T223	3		T291	1
all_values[17]	auto[0]	auto[0]	auto[0]	88	1			T221	2		T223	1		T224	3
all_values[17]	auto[0]	auto[1]	auto[0]	71	1			T221	1		T223	2		T224	3
all_values[17]	auto[1]	auto[0]	auto[1]	72	1			T221	3		T223	2		T224	1
all_values[17]	auto[1]	auto[1]	auto[1]	50	1			T221	1		T223	2		T291	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal