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 LINE       8941
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T42,T30
1	1	0	Not Covered
1	1	1	Covered	T28,T42,T30

 LINE       8942
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T29,T41
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T2,T29,T41

 LINE       8945
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T28
1	1	0	Covered	T214,T216,T252
1	1	1	Covered	T1,T3,T28

 LINE       8948
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T29,T32
1	1	0	Not Covered
1	1	1	Covered	T3,T29,T32

 LINE       8949
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T28,T42
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T3,T28,T42

 LINE       8974
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T29,T41
1	1	0	Covered	T214,T216,T252
1	1	1	Covered	T2,T29,T41

 LINE       8999
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T38
1	1	0	Covered	T214,T248,T252
1	1	1	Covered	T42,T43,T72

 LINE       9024
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T35,T36
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T33,T35,T36

 LINE       9049
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T164
1	1	0	Covered	T214,T248,T253
1	1	1	Covered	T42,T43,T164

 LINE       9074
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T31
1	1	0	Covered	T214,T252,T254
1	1	1	Covered	T42,T43,T31

 LINE       9099
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T38
1	1	0	Covered	T214,T216,T252
1	1	1	Covered	T32,T35,T8

 LINE       9110
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T38
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T32,T35,T17

 LINE       9121
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T4
1	1	0	Covered	T216,T252,T255
1	1	1	Covered	T32,T35,T108

 LINE       9132
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T43,T32
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T43,T32,T35

 LINE       9143
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T35,T36
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T35,T36,T5

 LINE       9154
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T35,T38
1	1	0	Covered	T214,T216,T251
1	1	1	Covered	T35,T161,T49

 LINE       9165
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T38
1	1	0	Covered	T214,T216,T251
1	1	1	Covered	T32,T35,T85

 LINE       9176
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T33,T35
1	1	0	Covered	T215,T216,T252
1	1	1	Covered	T31,T33,T35

 LINE       9187
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T118,T60
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T35,T118,T60

 LINE       9198
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T71
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T32,T35,T4

 LINE       9209
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T38
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T32,T35,T171

 LINE       9220
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T34,T35
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T29,T34,T35

 LINE       9231
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T30,T43
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T42,T30,T43

 LINE       9256
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T36
1	1	0	Covered	T214,T255,T256
1	1	1	Covered	T42,T43,T36

 LINE       9281
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T32,T37
1	1	0	Not Covered
1	1	1	Covered	T32,T108,T114

 LINE       9282
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T32,T37
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T29,T32,T37

 LINE       9287
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T43,T32
1	1	0	Not Covered
1	1	1	Covered	T32,T60,T108

 LINE       9288
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T43,T32
1	1	0	Covered	T214,T248,T252
1	1	1	Covered	T29,T32,T109

 LINE       9293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T38,T82
1	1	0	Covered	T257
1	1	1	Covered	T40,T25,T229

 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T25,T172
1	1	0	Covered	T214,T216,T248
1	1	1	Covered	T25,T26,T27

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T1,T2,T3

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T71,T7
1	1	0	Covered	T216,T248,T255
1	1	1	Covered	T7,T8,T9

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T42,T43,T32
1	1	0	Covered	T214,T254,T255
1	1	1	Covered	T42,T43,T32

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T212,T109
1	1	0	Not Covered
1	1	1	Covered	T222,T236,T247

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T212,T109
1	1	0	Covered	T214,T216,T251
1	1	1	Covered	T222,T236,T247

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T38,T212
1	1	0	Not Covered
1	1	1	Covered	T222,T236,T247

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T38,T212
1	1	0	Covered	T216,T248,T252
1	1	1	Covered	T222,T236,T247

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T249,T109
1	1	0	Not Covered
1	1	1	Covered	T222,T236,T247

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T249,T109
1	1	0	Covered	T214,T252,T253
1	1	1	Covered	T222,T236,T247

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T38,T109
1	1	0	Not Covered
1	1	1	Covered	T222,T236,T247

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T38,T109
1	1	0	Covered	T214,T216,T252
1	1	1	Covered	T222,T236,T247

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T7,T8,T9