Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 10247814 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 10812007 1 T1 9 T2 8 T3 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 20409767 1 T1 192 T2 7 T3 10
values[0x0] 323672 1 T1 4 T2 3 T3 2
values[0x1] 326382 1 T1 9 T2 4 T3 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8148695 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 12911126 1 T1 72 T2 10 T3 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 129136 1 T1 2 T22 1 T7 3
valid_sources[0x01] 62283 1 T3 1 T22 2 T7 5
valid_sources[0x02] 61167 1 T19 11 T7 9 T28 4
valid_sources[0x03] 75839 1 T1 1 T7 3 T28 9
valid_sources[0x04] 77625 1 T22 1 T7 5 T28 6
valid_sources[0x05] 91307 1 T1 1 T28 5 T85 138
valid_sources[0x06] 62464 1 T1 2 T7 4 T28 4
valid_sources[0x07] 101837 1 T16 1 T7 3 T28 6
valid_sources[0x08] 64370 1 T7 1 T28 9 T85 81
valid_sources[0x09] 83366 1 T1 7 T7 1 T27 2
valid_sources[0x0a] 62299 1 T1 3 T27 2 T28 7
valid_sources[0x0b] 62685 1 T35 1 T28 2 T85 134
valid_sources[0x0c] 72562 1 T22 1 T7 2 T28 8
valid_sources[0x0d] 61704 1 T1 1 T7 2 T27 1
valid_sources[0x0e] 64168 1 T84 1 T28 7 T29 2
valid_sources[0x0f] 62840 1 T1 1 T27 1 T28 2
valid_sources[0x10] 61120 1 T7 6 T60 1 T27 1
valid_sources[0x11] 62164 1 T7 4 T27 4 T28 2
valid_sources[0x12] 63252 1 T7 9 T28 8 T59 1
valid_sources[0x13] 74259 1 T1 1 T7 6 T28 5
valid_sources[0x14] 61082 1 T1 5 T22 2 T7 3
valid_sources[0x15] 68441 1 T28 6 T85 115 T5 70
valid_sources[0x16] 76116 1 T3 1 T7 3 T28 5
valid_sources[0x17] 63968 1 T1 2 T19 6 T7 6
valid_sources[0x18] 61496 1 T7 2 T60 2 T27 1
valid_sources[0x19] 63280 1 T84 1 T7 1 T27 1
valid_sources[0x1a] 63743 1 T7 2 T27 3 T28 4
valid_sources[0x1b] 102574 1 T1 8 T7 1 T28 11
valid_sources[0x1c] 153121 1 T7 3 T27 1 T28 7
valid_sources[0x1d] 63410 1 T7 3 T27 1 T28 5
valid_sources[0x1e] 62758 1 T18 111 T7 8 T28 4
valid_sources[0x1f] 63493 1 T1 1 T7 1 T28 5
valid_sources[0x20] 105503 1 T1 3 T7 6 T28 5
valid_sources[0x21] 165183 1 T1 5 T19 10 T28 5
valid_sources[0x22] 63584 1 T22 1 T7 6 T27 2
valid_sources[0x23] 63725 1 T1 1 T22 1 T60 1
valid_sources[0x24] 63533 1 T1 1 T28 9 T29 1
valid_sources[0x25] 64632 1 T22 1 T7 4 T28 6
valid_sources[0x26] 62390 1 T22 1 T7 7 T28 2
valid_sources[0x27] 61584 1 T19 11 T7 4 T27 3
valid_sources[0x28] 63788 1 T20 15 T22 5 T27 1
valid_sources[0x29] 63503 1 T7 9 T28 6 T85 128
valid_sources[0x2a] 62420 1 T7 10 T28 4 T85 98
valid_sources[0x2b] 89007 1 T22 2 T84 3 T7 1
valid_sources[0x2c] 63666 1 T1 4 T17 1 T84 2
valid_sources[0x2d] 108826 1 T7 4 T28 5 T31 1
valid_sources[0x2e] 64430 1 T7 4 T28 10 T85 83
valid_sources[0x2f] 62100 1 T7 9 T28 6 T85 135
valid_sources[0x30] 62872 1 T1 2 T16 1 T22 1
valid_sources[0x31] 89602 1 T7 2 T27 2 T28 14
valid_sources[0x32] 151922 1 T27 3 T28 13 T30 1
valid_sources[0x33] 125395 1 T1 1 T22 1 T27 3
valid_sources[0x34] 63291 1 T22 1 T27 1 T28 8
valid_sources[0x35] 146741 1 T1 1 T7 6 T28 4
valid_sources[0x36] 63200 1 T1 1 T7 7 T27 1
valid_sources[0x37] 132420 1 T1 3 T7 3 T28 4
valid_sources[0x38] 70295 1 T1 2 T7 4 T27 4
valid_sources[0x39] 138261 1 T22 2 T7 3 T28 5
valid_sources[0x3a] 64965 1 T1 2 T22 1 T7 2
valid_sources[0x3b] 62258 1 T22 1 T7 1 T28 9
valid_sources[0x3c] 63779 1 T7 2 T27 3 T28 5
valid_sources[0x3d] 62345 1 T7 7 T27 2 T28 2
valid_sources[0x3e] 71908 1 T1 2 T7 4 T60 3
valid_sources[0x3f] 64855 1 T1 4 T16 1 T22 1
valid_sources[0x40] 77119 1 T7 9 T27 2 T28 9
valid_sources[0x41] 94977 1 T1 1 T7 2 T27 1
valid_sources[0x42] 339899 1 T1 1 T19 4 T7 1
valid_sources[0x43] 86408 1 T1 3 T22 1 T27 1
valid_sources[0x44] 127364 1 T22 2 T84 1 T7 1
valid_sources[0x45] 173048 1 T60 4 T27 2 T28 7
valid_sources[0x46] 62814 1 T84 1 T7 2 T28 3
valid_sources[0x47] 118741 1 T22 1 T7 6 T27 2
valid_sources[0x48] 63746 1 T7 1 T27 1 T28 3
valid_sources[0x49] 63237 1 T19 3 T22 3 T7 4
valid_sources[0x4a] 63170 1 T3 1 T22 1 T7 1
valid_sources[0x4b] 63369 1 T84 1 T7 5 T28 2
valid_sources[0x4c] 62295 1 T1 1 T7 10 T27 3
valid_sources[0x4d] 64364 1 T1 7 T19 4 T7 1
valid_sources[0x4e] 70494 1 T7 2 T27 3 T28 9
valid_sources[0x4f] 79243 1 T27 1 T28 2 T29 1
valid_sources[0x50] 109632 1 T22 2 T27 2 T28 5
valid_sources[0x51] 63943 1 T1 1 T7 1 T27 1
valid_sources[0x52] 64242 1 T3 3 T19 4 T22 2
valid_sources[0x53] 84413 1 T1 3 T22 3 T7 1
valid_sources[0x54] 75648 1 T7 2 T27 1 T28 5
valid_sources[0x55] 82045 1 T22 1 T7 8 T27 2
valid_sources[0x56] 61990 1 T7 1 T28 5 T85 145
valid_sources[0x57] 74757 1 T22 1 T7 2 T27 1
valid_sources[0x58] 78759 1 T7 1 T60 3 T28 3
valid_sources[0x59] 64211 1 T3 1 T7 1 T28 6
valid_sources[0x5a] 78571 1 T1 1 T7 2 T28 5
valid_sources[0x5b] 200222 1 T26 3090 T28 5 T85 124
valid_sources[0x5c] 62713 1 T1 3 T28 7 T29 1
valid_sources[0x5d] 62055 1 T19 2 T7 4 T28 11
valid_sources[0x5e] 151775 1 T1 4 T22 2 T7 4
valid_sources[0x5f] 77606 1 T17 4 T27 5 T28 8
valid_sources[0x60] 62078 1 T28 4 T85 107 T8 5
valid_sources[0x61] 63242 1 T1 1 T7 5 T28 5
valid_sources[0x62] 69426 1 T35 1 T7 3 T27 1
valid_sources[0x63] 62868 1 T7 7 T28 5 T31 1
valid_sources[0x64] 142322 1 T16 2 T28 1 T85 105
valid_sources[0x65] 104351 1 T7 6 T27 1 T28 10
valid_sources[0x66] 107105 1 T16 1 T7 2 T27 1
valid_sources[0x67] 79769 1 T19 3 T7 2 T28 5
valid_sources[0x68] 61624 1 T1 2 T22 2 T7 8
valid_sources[0x69] 63516 1 T7 1 T27 2 T28 7
valid_sources[0x6a] 65318 1 T22 1 T7 3 T28 3
valid_sources[0x6b] 202652 1 T1 3 T84 1 T7 6
valid_sources[0x6c] 84408 1 T19 4 T60 1 T27 1
valid_sources[0x6d] 63191 1 T7 1 T27 3 T28 7
valid_sources[0x6e] 62637 1 T27 1 T28 4 T85 102
valid_sources[0x6f] 63163 1 T7 2 T27 2 T28 8
valid_sources[0x70] 67020 1 T19 5 T27 1 T28 6
valid_sources[0x71] 178548 1 T1 2 T7 7 T27 2
valid_sources[0x72] 81861 1 T1 2 T7 1 T27 2
valid_sources[0x73] 63277 1 T19 6 T7 10 T27 1
valid_sources[0x74] 109989 1 T7 3 T27 1 T28 5
valid_sources[0x75] 61730 1 T28 5 T85 151 T5 195
valid_sources[0x76] 131138 1 T22 1 T7 1 T27 1
valid_sources[0x77] 72910 1 T7 1 T28 7 T36 1
valid_sources[0x78] 62682 1 T35 1 T7 8 T27 3
valid_sources[0x79] 62712 1 T1 1 T7 4 T27 2
valid_sources[0x7a] 61371 1 T7 4 T27 3 T85 120
valid_sources[0x7b] 80008 1 T7 8 T28 2 T31 1
valid_sources[0x7c] 84862 1 T19 9 T7 1 T27 1
valid_sources[0x7d] 64659 1 T7 7 T85 132 T5 63
valid_sources[0x7e] 62461 1 T7 7 T27 2 T28 4
valid_sources[0x7f] 76957 1 T22 2 T7 2 T28 7
valid_sources[0x80] 63116 1 T16 3 T7 1 T85 121



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 10288139 1 T1 2 T2 6 T16 3
values[0x0] all_enables biggest_size 269786 1 T1 4 T2 1 T3 1
values[0x1] all_enables biggest_size 254082 1 T1 3 T2 1 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%