Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

10261353

1

T1

196

T2

6

T3

17

full_word

10812948

1

T1

9

T2

8

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	21074001	1			T1	205		T2	14		T3	20
auto[TlIntgErrCmd]	101	1			T234	1		T235	4		T236	3
auto[TlIntgErrData]	105	1			T234	4		T235	9		T236	3
auto[TlIntgErrBoth]	94	1			T234	5		T235	7		T236	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20411670

1

T1

192

T2

7

T3

10

auto[1]

662631

1

T1

13

T2

7

T3

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	10123238	1			T1	190		T2	1		T3	10
auto[TlIntgErrNone]	partial	auto[1]	137836	1			T1	6		T2	5		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	10288309	1			T1	2		T2	6		T16	3
auto[TlIntgErrNone]	full_word	auto[1]	524618	1			T1	7		T2	2		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T235	2		T236	2		T444	6
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T234	1		T235	2		T444	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T445	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T236	1		T449	1		-	-
auto[TlIntgErrData]	partial	auto[0]	34	1			T235	2		T444	1		T450	3
auto[TlIntgErrData]	partial	auto[1]	62	1			T234	4		T235	6		T236	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T235	1		T236	1		T444	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T447	1		T451	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T234	1		T235	4		T236	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T234	3		T235	3		T236	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T449	1		T452	1		T453	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T234	1		T444	1		T449	1