Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	576493221	11289	0	0
ep_in_enable_rd_A	576493221	4499	0	0
ep_out_enable_rd_A	576493221	4376	0	0
in_iso_rd_A	576493221	4130	0	0
intr_enable_rd_A	576493221	5022	0	0
out_iso_rd_A	576493221	4341	0	0
phy_config_rd_A	576493221	2482	0	0
phy_pins_drive_rd_A	576493221	3441	0	0
rxenable_setup_rd_A	576493221	4252	0	0
set_nak_out_rd_A	576493221	3879	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	11289	0	0
T210	3679	9	0	0
T211	15445	926	0	0
T212	3222	11	0	0
T228	16258	686	0	0
T229	4346	241	0	0
T234	20130	4	0	0
T235	42671	4	0	0
T236	24344	5	0	0
T242	5900	768	0	0
T246	4851	9	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	4499	0	0
T218	4628	3	0	0
T231	11966	34	0	0
T234	20130	194	0	0
T235	42671	654	0	0
T236	24344	223	0	0
T261	2406	34	0	0
T262	10103	84	0	0
T266	4203	27	0	0
T276	2471	2	0	0
T277	8949	13	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	4376	0	0
T218	4628	7	0	0
T228	16258	1	0	0
T231	11966	41	0	0
T234	20130	133	0	0
T235	42671	636	0	0
T236	24344	220	0	0
T261	2406	18	0	0
T262	10103	104	0	0
T276	2471	1	0	0
T277	8949	38	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	4130	0	0
T218	4628	5	0	0
T231	11966	34	0	0
T234	20130	180	0	0
T235	42671	409	0	0
T236	24344	284	0	0
T248	8003	33	0	0
T262	10103	113	0	0
T266	4203	38	0	0
T276	2471	39	0	0
T277	8949	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	5022	0	0
T211	15445	9	0	0
T231	11966	44	0	0
T234	20130	205	0	0
T235	42671	714	0	0
T236	24344	222	0	0
T262	10103	79	0	0
T266	4203	37	0	0
T276	2471	77	0	0
T277	8949	11	0	0
T278	6958	18	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	4341	0	0
T231	11966	33	0	0
T234	20130	96	0	0
T235	42671	557	0	0
T236	24344	298	0	0
T261	2406	25	0	0
T262	10103	84	0	0
T266	4203	27	0	0
T276	2471	6	0	0
T277	8949	45	0	0
T278	6958	7	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	2482	0	0
T218	4628	6	0	0
T231	11966	35	0	0
T234	20130	60	0	0
T235	42671	189	0	0
T236	24344	124	0	0
T262	10103	97	0	0
T266	4203	23	0	0
T276	2471	27	0	0
T277	8949	20	0	0
T278	6958	15	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	3441	0	0
T218	4628	8	0	0
T228	16258	3	0	0
T231	11966	52	0	0
T234	20130	69	0	0
T235	42671	459	0	0
T236	24344	210	0	0
T261	2406	11	0	0
T262	10103	81	0	0
T276	2471	2	0	0
T277	8949	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	4252	0	0
T218	4628	8	0	0
T231	11966	64	0	0
T234	20130	141	0	0
T235	42671	569	0	0
T236	24344	272	0	0
T261	2406	4	0	0
T262	10103	104	0	0
T266	4203	39	0	0
T276	2471	46	0	0
T277	8949	11	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576493221	3879	0	0
T218	4628	2	0	0
T228	16258	4	0	0
T231	11966	67	0	0
T234	20130	37	0	0
T235	42671	590	0	0
T236	24344	191	0	0
T261	2406	36	0	0
T262	10103	83	0	0
T276	2471	6	0	0
T277	8949	24	0	0