Module Definition
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Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_req_d_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_req_d_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_write_d_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_write_d_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_req_d_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_write_d_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3