Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83773	1			T1	3		T2	4		T3	7
all_values[1]	83773	1			T1	3		T2	4		T3	7
all_values[2]	83773	1			T1	3		T2	4		T3	7
all_values[3]	83773	1			T1	3		T2	4		T3	7
all_values[4]	83773	1			T1	3		T2	4		T3	7
all_values[5]	83773	1			T1	3		T2	4		T3	7
all_values[6]	83773	1			T1	3		T2	4		T3	7
all_values[7]	83773	1			T1	3		T2	4		T3	7
all_values[8]	83773	1			T1	3		T2	4		T3	7
all_values[9]	83773	1			T1	3		T2	4		T3	7
all_values[10]	83773	1			T1	3		T2	4		T3	7
all_values[11]	83773	1			T1	3		T2	4		T3	7
all_values[12]	83773	1			T1	3		T2	4		T3	7
all_values[13]	83773	1			T1	3		T2	4		T3	7
all_values[14]	83773	1			T1	3		T2	4		T3	7
all_values[15]	83773	1			T1	3		T2	4		T3	7
all_values[16]	83773	1			T1	3		T2	4		T3	7
all_values[17]	83773	1			T1	3		T2	4		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2670703

1

T1

94

T2

128

T3

219

auto[1]

10033

1

T1

2

T3

5

T29

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2231097

1

T1

85

T2

110

T3

210

auto[1]

449639

1

T1

11

T2

18

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55498	1			T1	3		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	24961	1			T2	1		T29	3		T33	2
all_values[0]	auto[1]	auto[0]	3213	1			T48	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	101	1			T231	1		T399	1		T400	1
all_values[1]	auto[0]	auto[0]	79267	1			T1	3		T2	4		T3	7
all_values[1]	auto[0]	auto[1]	3113	1			T31	2		T32	2		T36	1
all_values[1]	auto[1]	auto[0]	524	1			T34	2		T38	2		T52	2
all_values[1]	auto[1]	auto[1]	869	1			T34	12		T38	1		T52	1
all_values[2]	auto[0]	auto[0]	4400	1			T1	1		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	79094	1			T1	2		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	154	1			T40	1		T65	1		T66	1
all_values[2]	auto[1]	auto[1]	125	1			T40	1		T65	1		T66	1
all_values[3]	auto[0]	auto[0]	81818	1			T1	3		T2	4		T3	7
all_values[3]	auto[0]	auto[1]	300	1			T49	1		T67	1		T68	1
all_values[3]	auto[1]	auto[0]	1569	1			T49	1483		T220	1		T221	2
all_values[3]	auto[1]	auto[1]	86	1			T49	1		T220	3		T221	4
all_values[4]	auto[0]	auto[0]	4381	1			T1	1		T2	1		T3	6
all_values[4]	auto[0]	auto[1]	79216	1			T1	2		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	111	1			T18	1		T220	1		T221	3
all_values[4]	auto[1]	auto[1]	65	1			T18	1		T221	2		T224	1
all_values[5]	auto[0]	auto[0]	83217	1			T1	3		T2	4		T3	7
all_values[5]	auto[0]	auto[1]	354	1			T7	1		T8	1		T62	1
all_values[5]	auto[1]	auto[0]	128	1			T221	5		T222	5		T224	7
all_values[5]	auto[1]	auto[1]	74	1			T221	1		T224	1		T225	1
all_values[6]	auto[0]	auto[0]	83334	1			T1	3		T2	4		T3	7
all_values[6]	auto[0]	auto[1]	214	1			T7	1		T8	1		T62	1
all_values[6]	auto[1]	auto[0]	109	1			T220	1		T221	3		T224	3
all_values[6]	auto[1]	auto[1]	116	1			T69	1		T70	1		T71	1
all_values[7]	auto[0]	auto[0]	28417	1			T1	3		T40	2		T41	2
all_values[7]	auto[0]	auto[1]	55170	1			T2	4		T3	7		T29	6
all_values[7]	auto[1]	auto[0]	118	1			T53	2		T220	1		T221	4
all_values[7]	auto[1]	auto[1]	68	1			T53	1		T221	1		T222	2
all_values[8]	auto[0]	auto[0]	82840	1			T1	3		T2	4		T3	7
all_values[8]	auto[0]	auto[1]	244	1			T33	2		T37	2		T176	2
all_values[8]	auto[1]	auto[0]	598	1			T55	10		T56	10		T57	10
all_values[8]	auto[1]	auto[1]	91	1			T56	1		T58	1		T59	1
all_values[9]	auto[0]	auto[0]	83495	1			T1	3		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	69	1			T221	3		T222	1		T224	1
all_values[9]	auto[1]	auto[0]	140	1			T3	3		T63	3		T64	3
all_values[9]	auto[1]	auto[1]	69	1			T3	2		T63	2		T64	2
all_values[10]	auto[0]	auto[0]	83169	1			T1	3		T2	4		T3	7
all_values[10]	auto[0]	auto[1]	420	1			T32	1		T35	1		T19	2
all_values[10]	auto[1]	auto[0]	118	1			T221	2		T222	1		T224	3
all_values[10]	auto[1]	auto[1]	66	1			T221	2		T225	2		T293	1
all_values[11]	auto[0]	auto[0]	82783	1			T1	2		T2	4		T3	7
all_values[11]	auto[0]	auto[1]	710	1			T1	1		T17	4		T20	4
all_values[11]	auto[1]	auto[0]	166	1			T73	1		T74	1		T75	1
all_values[11]	auto[1]	auto[1]	114	1			T73	1		T74	1		T75	1
all_values[12]	auto[0]	auto[0]	83363	1			T1	3		T2	4		T3	7
all_values[12]	auto[0]	auto[1]	211	1			T78	3		T80	1		T81	1
all_values[12]	auto[1]	auto[0]	131	1			T76	2		T77	2		T79	2
all_values[12]	auto[1]	auto[1]	68	1			T76	1		T77	1		T79	1
all_values[13]	auto[0]	auto[0]	83423	1			T1	1		T2	4		T3	7
all_values[13]	auto[0]	auto[1]	75	1			T80	1		T81	1		T84	1
all_values[13]	auto[1]	auto[0]	148	1			T1	1		T82	1		T83	1
all_values[13]	auto[1]	auto[1]	127	1			T1	1		T82	1		T83	1
all_values[14]	auto[0]	auto[0]	16825	1			T1	3		T2	4		T3	7
all_values[14]	auto[0]	auto[1]	66781	1			T40	1		T7	2		T49	1485
all_values[14]	auto[1]	auto[0]	108	1			T221	3		T222	2		T224	1
all_values[14]	auto[1]	auto[1]	59	1			T221	1		T224	5		T293	3
all_values[15]	auto[0]	auto[0]	4434	1			T1	1		T2	1		T3	6
all_values[15]	auto[0]	auto[1]	79142	1			T1	2		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	105	1			T220	1		T221	3		T222	1
all_values[15]	auto[1]	auto[1]	92	1			T220	1		T221	2		T222	3
all_values[16]	auto[0]	auto[0]	82676	1			T1	3		T2	4		T3	7
all_values[16]	auto[0]	auto[1]	886	1			T32	1		T33	1		T72	1
all_values[16]	auto[1]	auto[0]	134	1			T17	4		T20	4		T25	4
all_values[16]	auto[1]	auto[1]	77	1			T17	4		T20	4		T25	4
all_values[17]	auto[0]	auto[0]	27240	1			T3	5		T29	1		T41	2
all_values[17]	auto[0]	auto[1]	56341	1			T1	3		T2	4		T3	2
all_values[17]	auto[1]	auto[0]	121	1			T29	2		T60	2		T61	2
all_values[17]	auto[1]	auto[1]	71	1			T29	1		T60	1		T61	1