Name |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2460751318 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3249446545 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.1296588676 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.2769958763 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.549771755 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2368725892 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3089055530 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.1896277542 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.2049253169 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3972338123 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.246488083 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2726386784 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.3093568886 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.2603869607 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4280753141 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.2166526745 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3590350931 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.145397240 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.4281037697 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.570058176 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.1622403964 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.3570132581 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2742374085 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.1244335060 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2026962976 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.155732545 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3805393073 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.2402869717 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.3770389993 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2680425019 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.3326531551 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1946748873 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.568808294 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.3177968446 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.587092623 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2530175903 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3505139934 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1611529568 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.2326880151 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4072964690 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.2037017792 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.1793106409 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.841818052 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.343039371 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.3836268396 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2978838427 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.939588989 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.67525099 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1758080856 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.889634936 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.1470127596 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2018867540 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.3771123188 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.915570591 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.4160806276 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1344928866 |
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/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.2277330763 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4195375936 |
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.530856805 |
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