Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1926	1			T67	5		T107	569		T409	1
range_16_to_126	147156	1			T29	1		T30	1		T31	5
fifteen	2456	1			T41	1		T243	3		T67	2
range_2_to_14	22356	1			T2	1		T41	2		T42	1
seven	2352	1			T67	3		T78	9		T120	4
one	2248	1			T41	1		T67	4		T120	2
zero	1754	1			T1	1		T82	1		T230	5

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

11370

1

T32

1

T34

2

T22

2

three

12979

1

T42

1

T32

1

T34

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	161	1			T107	49		T180	2		T121	2
range_127	three	155	1			T107	56		T410	2		T411	1
range_16_to_126	seven	9829	1			T32	1		T34	2		T22	2
range_16_to_126	three	11065	1			T42	1		T32	1		T34	2
fifteen	seven	152	1			T121	1		T412	1		T413	35
fifteen	three	174	1			T414	1		T413	24		T415	2
range_2_to_14	seven	1064	1			T67	6		T162	2		T120	3
range_2_to_14	three	1405	1			T112	21		T67	1		T119	1
seven	seven	95	1			T416	9		T417	1		T418	1
seven	three	97	1			T120	1		T419	1		T420	15
one	seven	76	1			T421	1		T422	1		T423	2
one	three	87	1			T184	1		T413	1		T424	1
zero	seven	88	1			T425	1		T184	1		T426	1
zero	three	93	1			T180	1		T121	1		T427	2