Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
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Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_crc5 3 0 3 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc5_X_dir 6 0 6 100.00 100 1 1 0


Summary for Variable cp_crc5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_crc5

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_ones 4690 1 T41 3 T34 2 T72 2
leading_zero 4567 1 T41 1 T32 2 T60 1
trailing_zero 6386 1 T30 1 T32 2 T87 1



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 110822 1 T1 1 T2 1 T29 1
auto[1] 67074 1 T30 1 T31 4 T41 14



Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for cr_crc5_X_dir

Bins
cp_crc5   cp_dir   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_ones auto[0] 2726 1 T41 1 T34 1 T72 2
all_ones auto[1] 1964 1 T41 2 T34 1 T48 1
leading_zero auto[0] 2540 1 T32 1 T60 1 T67 10
leading_zero auto[1] 2027 1 T41 1 T32 1 T67 10
trailing_zero auto[0] 4199 1 T32 2 T87 1 T67 10
trailing_zero auto[1] 2187 1 T30 1 T67 6 T107 25