Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110680

1

T1

1

T2

1

T29

1

auto[1]

45124

1

T30

1

T31

4

T32

11

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28976	1			T21	1		T22	2		T49	2
max_len_m1	879	1			T20	1		T49	2		T54	1
max_len_m2	797	1			T34	2		T49	2		T111	1
max_len_m3	900	1			T17	1		T166	1		T49	2
five	1214	1			T17	1		T54	1		T5	2
four	1186	1			T34	2		T49	3		T112	4
three	708	1			T34	2		T25	1		T49	2
one	835	1			T17	1		T49	3		T55	1
zero	11271	1			T1	1		T30	1		T31	4

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23542	1			T21	1		T22	1		T49	2
max_len	auto[1]	5434	1			T22	1		T4	1		T5	2
max_len_m1	auto[0]	594	1			T20	1		T49	2		T54	1
max_len_m1	auto[1]	285	1			T5	2		T164	1		T68	2
max_len_m2	auto[0]	534	1			T34	1		T49	2		T111	1
max_len_m2	auto[1]	263	1			T34	1		T4	1		T164	4
max_len_m3	auto[0]	595	1			T17	1		T166	1		T49	2
max_len_m3	auto[1]	305	1			T93	1		T5	1		T164	1
five	auto[0]	624	1			T17	1		T54	1		T5	1
five	auto[1]	590	1			T5	1		T164	1		T161	1
four	auto[0]	619	1			T34	1		T49	3		T112	2
four	auto[1]	567	1			T34	1		T112	2		T164	2
three	auto[0]	352	1			T34	1		T25	1		T49	2
three	auto[1]	356	1			T34	1		T113	1		T107	9
one	auto[0]	387	1			T17	1		T49	3		T55	1
one	auto[1]	448	1			T69	1		T434	1		T107	8
zero	auto[0]	501	1			T1	1		T23	1		T24	1
zero	auto[1]	10770	1			T30	1		T31	4		T32	3