Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136416

1

T2

2

T29

2

T31

2

auto[1]

76751

1

T30

2

T31

8

T32

17

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	26378	1			T29	2		T34	4		T54	2
endpoints[0x1]	14117	1			T30	2		T32	3		T34	4
endpoints[0x2]	15433	1			T32	3		T34	4		T50	6
endpoints[0x3]	17117	1			T32	2		T34	4		T35	3
endpoints[0x4]	17736	1			T32	9		T34	4		T25	21
endpoints[0x5]	20127	1			T32	6		T34	4		T17	21
endpoints[0x6]	15389	1			T32	4		T34	4		T160	4
endpoints[0x7]	14167	1			T32	2		T34	4		T22	4
endpoints[0x8]	17852	1			T32	4		T34	4		T37	16
endpoints[0x9]	15329	1			T2	2		T31	10		T34	4
endpoints[0xa]	18874	1			T32	2		T33	17		T34	4
endpoints[0xb]	20648	1			T32	4		T34	4		T36	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1295	1			T32	2		T17	2		T20	2
ack	103158	1			T2	1		T29	1		T30	1
data1	50094	1			T31	1		T32	10		T17	5
data0	58547	1			T2	1		T29	1		T30	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	104	1			T120	6		T180	4		T184	11
nak	auto[0]	endpoints[0x1]	115	1			T54	1		T126	1		T435	1
nak	auto[0]	endpoints[0x2]	76	1			T121	6		T132	1		T436	1
nak	auto[0]	endpoints[0x3]	95	1			T180	14		T135	1		T136	1
nak	auto[0]	endpoints[0x4]	98	1			T25	2		T180	7		T437	1
nak	auto[0]	endpoints[0x5]	59	1			T17	2		T72	1		T120	2
nak	auto[0]	endpoints[0x6]	87	1			T438	1		T121	12		T340	1
nak	auto[0]	endpoints[0x7]	99	1			T244	1		T186	7		T439	5
nak	auto[0]	endpoints[0x8]	86	1			T440	1		T148	1		T441	1
nak	auto[0]	endpoints[0x9]	107	1			T184	8		T426	12		T442	1
nak	auto[0]	endpoints[0xa]	83	1			T20	2		T67	7		T443	1
nak	auto[0]	endpoints[0xb]	100	1			T67	10		T120	6		T444	1
nak	auto[1]	endpoints[0x0]	13	1			T445	1		T446	1		T447	1
nak	auto[1]	endpoints[0x1]	11	1			T448	1		T449	1		T450	1
nak	auto[1]	endpoints[0x2]	7	1			T445	1		T451	1		T447	1
nak	auto[1]	endpoints[0x3]	22	1			T32	1		T118	3		T448	1
nak	auto[1]	endpoints[0x4]	13	1			T118	1		T452	1		T453	3
nak	auto[1]	endpoints[0x5]	15	1			T32	1		T113	1		T445	1
nak	auto[1]	endpoints[0x6]	25	1			T118	1		T448	1		T454	2
nak	auto[1]	endpoints[0x7]	13	1			T118	1		T455	2		T453	1
nak	auto[1]	endpoints[0x8]	15	1			T451	1		T446	1		T454	2
nak	auto[1]	endpoints[0x9]	14	1			T113	1		T448	1		T445	1
nak	auto[1]	endpoints[0xa]	18	1			T118	1		T448	1		T451	1
nak	auto[1]	endpoints[0xb]	20	1			T448	1		T455	1		T451	1
ack	auto[0]	endpoints[0x0]	9668	1			T29	1		T34	1		T54	1
ack	auto[0]	endpoints[0x1]	3955	1			T32	1		T34	1		T456	1
ack	auto[0]	endpoints[0x2]	4370	1			T32	1		T34	1		T50	2
ack	auto[0]	endpoints[0x3]	4784	1			T34	1		T19	1		T24	1
ack	auto[0]	endpoints[0x4]	5423	1			T32	1		T34	1		T25	8
ack	auto[0]	endpoints[0x5]	6512	1			T32	1		T34	1		T17	8
ack	auto[0]	endpoints[0x6]	4344	1			T32	1		T34	1		T160	1
ack	auto[0]	endpoints[0x7]	3936	1			T32	1		T34	1		T22	1
ack	auto[0]	endpoints[0x8]	5315	1			T32	2		T34	1		T37	8
ack	auto[0]	endpoints[0x9]	3887	1			T2	1		T31	1		T34	1
ack	auto[0]	endpoints[0xa]	6249	1			T32	1		T33	8		T34	1
ack	auto[0]	endpoints[0xb]	6943	1			T32	2		T34	1		T36	1
ack	auto[1]	endpoints[0x0]	3244	1			T34	1		T4	5		T93	1
ack	auto[1]	endpoints[0x1]	2775	1			T30	1		T34	1		T159	2
ack	auto[1]	endpoints[0x2]	3070	1			T34	1		T50	1		T4	5
ack	auto[1]	endpoints[0x3]	3501	1			T34	1		T35	1		T24	1
ack	auto[1]	endpoints[0x4]	3183	1			T32	3		T34	1		T48	1
ack	auto[1]	endpoints[0x5]	3249	1			T34	1		T51	1		T52	1
ack	auto[1]	endpoints[0x6]	3058	1			T32	1		T34	1		T160	1
ack	auto[1]	endpoints[0x7]	2814	1			T34	1		T22	1		T161	7
ack	auto[1]	endpoints[0x8]	3335	1			T34	1		T163	1		T4	5
ack	auto[1]	endpoints[0x9]	3493	1			T31	4		T34	1		T112	10
ack	auto[1]	endpoints[0xa]	2909	1			T34	1		T62	1		T69	1
ack	auto[1]	endpoints[0xb]	3141	1			T34	1		T38	1		T4	5
data1	auto[0]	endpoints[0x0]	4525	1			T4	2		T93	1		T159	1
data1	auto[0]	endpoints[0x1]	1711	1			T54	4		T159	2		T5	3
data1	auto[0]	endpoints[0x2]	1883	1			T50	1		T4	2		T161	2
data1	auto[0]	endpoints[0x3]	2079	1			T55	3		T4	2		T112	4
data1	auto[0]	endpoints[0x4]	2403	1			T32	1		T25	5		T48	1
data1	auto[0]	endpoints[0x5]	3024	1			T32	1		T17	5		T72	1
data1	auto[0]	endpoints[0x6]	1898	1			T113	1		T112	4		T107	16
data1	auto[0]	endpoints[0x7]	1690	1			T113	1		T161	3		T68	6
data1	auto[0]	endpoints[0x8]	2388	1			T32	1		T163	1		T4	1
data1	auto[0]	endpoints[0x9]	1633	1			T114	1		T113	1		T112	4
data1	auto[0]	endpoints[0xa]	2818	1			T32	1		T20	5		T94	5
data1	auto[0]	endpoints[0xb]	3190	1			T32	2		T4	1		T67	10
data1	auto[1]	endpoints[0x0]	1768	1			T4	2		T93	1		T159	1
data1	auto[1]	endpoints[0x1]	1504	1			T32	1		T159	2		T5	9
data1	auto[1]	endpoints[0x2]	1654	1			T32	1		T50	1		T4	3
data1	auto[1]	endpoints[0x3]	1985	1			T32	1		T4	2		T112	5
data1	auto[1]	endpoints[0x4]	1776	1			T48	1		T4	2		T161	3
data1	auto[1]	endpoints[0x5]	1793	1			T32	1		T51	1		T4	4
data1	auto[1]	endpoints[0x6]	1712	1			T5	6		T113	3		T112	4
data1	auto[1]	endpoints[0x7]	1553	1			T161	3		T68	6		T107	11
data1	auto[1]	endpoints[0x8]	1835	1			T163	1		T4	4		T5	7
data1	auto[1]	endpoints[0x9]	1940	1			T31	1		T113	2		T112	5
data1	auto[1]	endpoints[0xa]	1568	1			T113	1		T161	3		T187	6
data1	auto[1]	endpoints[0xb]	1764	1			T4	4		T191	1		T107	13
data0	auto[0]	endpoints[0x0]	5476	1			T29	1		T34	1		T54	1
data0	auto[0]	endpoints[0x1]	2715	1			T32	1		T34	1		T456	1
data0	auto[0]	endpoints[0x2]	2867	1			T32	1		T34	1		T50	1
data0	auto[0]	endpoints[0x3]	3012	1			T34	1		T19	1		T24	1
data0	auto[0]	endpoints[0x4]	3369	1			T34	1		T25	6		T48	1
data0	auto[0]	endpoints[0x5]	3923	1			T34	1		T17	6		T72	1
data0	auto[0]	endpoints[0x6]	2809	1			T32	1		T34	1		T160	1
data0	auto[0]	endpoints[0x7]	2721	1			T32	1		T34	1		T22	1
data0	auto[0]	endpoints[0x8]	3312	1			T32	1		T34	1		T37	8
data0	auto[0]	endpoints[0x9]	2623	1			T2	1		T31	1		T34	1
data0	auto[0]	endpoints[0xa]	3813	1			T33	9		T34	1		T20	6
data0	auto[0]	endpoints[0xb]	4016	1			T34	1		T36	1		T38	1
data0	auto[1]	endpoints[0x0]	1571	1			T34	1		T4	3		T162	1
data0	auto[1]	endpoints[0x1]	1327	1			T30	1		T34	1		T5	4
data0	auto[1]	endpoints[0x2]	1504	1			T34	1		T4	2		T113	1
data0	auto[1]	endpoints[0x3]	1632	1			T34	1		T35	2		T19	1
data0	auto[1]	endpoints[0x4]	1463	1			T32	4		T34	1		T4	3
data0	auto[1]	endpoints[0x5]	1543	1			T32	2		T34	1		T52	1
data0	auto[1]	endpoints[0x6]	1449	1			T32	1		T34	1		T160	1
data0	auto[1]	endpoints[0x7]	1339	1			T34	1		T22	1		T161	4
data0	auto[1]	endpoints[0x8]	1561	1			T34	1		T4	1		T5	6
data0	auto[1]	endpoints[0x9]	1626	1			T31	3		T34	1		T112	5
data0	auto[1]	endpoints[0xa]	1412	1			T34	1		T62	1		T69	1
data0	auto[1]	endpoints[0xb]	1464	1			T34	1		T38	1		T4	1