Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8411 1 T41 2 T42 1 T243 4
auto[1] 53364 1 T30 1 T31 4 T41 12


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54045 1 T30 1 T31 4 T41 14
auto[1] 7730 1 T42 1 T36 1 T5 28


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55867 1 T30 1 T31 4 T41 3
auto[1] 5908 1 T41 11 T43 1 T111 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4440 1 T41 5 T243 1 T67 68
pkt_types[PidTypeInToken] 57335 1 T30 1 T31 4 T41 9


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1441 1 T243 1 T67 40 T120 33
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 666 1 T67 1 T120 6 T457 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 97 1 T458 4 T411 3 T414 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 19 1 T459 1 T460 1 T461 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1368 1 T41 2 T67 19 T120 13
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 732 1 T41 3 T67 8 T120 9
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 94 1 T462 1 T458 1 T411 3
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 23 1 T461 2 T463 3 T464 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4033 1 T243 3 T67 88 T119 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2057 1 T41 2 T120 23 T457 6
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 49 1 T42 1 T465 1 T459 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 49 1 T119 2 T465 1 T459 2
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41442 1 T30 1 T31 4 T41 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2306 1 T41 6 T43 1 T111 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7343 1 T36 1 T5 28 T6 44
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 56 1 T466 1 T467 1 T468 1

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