Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83773	1			T1	3		T2	4		T3	7
all_pins[1]	83773	1			T1	3		T2	4		T3	7
all_pins[2]	83773	1			T1	3		T2	4		T3	7
all_pins[3]	83773	1			T1	3		T2	4		T3	7
all_pins[4]	83773	1			T1	3		T2	4		T3	7
all_pins[5]	83773	1			T1	3		T2	4		T3	7
all_pins[6]	83773	1			T1	3		T2	4		T3	7
all_pins[7]	83773	1			T1	3		T2	4		T3	7
all_pins[8]	83773	1			T1	3		T2	4		T3	7
all_pins[9]	83773	1			T1	3		T2	4		T3	7
all_pins[10]	83773	1			T1	3		T2	4		T3	7
all_pins[11]	83773	1			T1	3		T2	4		T3	7
all_pins[12]	83773	1			T1	3		T2	4		T3	7
all_pins[13]	83773	1			T1	3		T2	4		T3	7
all_pins[14]	83773	1			T1	3		T2	4		T3	7
all_pins[15]	83773	1			T1	3		T2	4		T3	7
all_pins[16]	83773	1			T1	3		T2	4		T3	7
all_pins[17]	83773	1			T1	3		T2	4		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2678398	1			T1	95		T2	128		T3	222
values[0x1]	2338	1			T1	1		T3	2		T29	1
transitions[0x0=>0x1]	2029	1			T1	1		T3	2		T29	1
transitions[0x1=>0x0]	2029	1			T1	1		T3	2		T29	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	83672	1			T1	3		T2	4		T3	7
all_pins[0]	values[0x1]	101	1			T231	1		T399	1		T400	1
all_pins[0]	transitions[0x0=>0x1]	86	1			T231	1		T399	1		T400	1
all_pins[0]	transitions[0x1=>0x0]	854	1			T34	12		T38	1		T52	1
all_pins[1]	values[0x0]	82904	1			T1	3		T2	4		T3	7
all_pins[1]	values[0x1]	869	1			T34	12		T38	1		T52	1
all_pins[1]	transitions[0x0=>0x1]	857	1			T34	12		T38	1		T52	1
all_pins[1]	transitions[0x1=>0x0]	113	1			T40	1		T65	1		T66	1
all_pins[2]	values[0x0]	83648	1			T1	3		T2	4		T3	7
all_pins[2]	values[0x1]	125	1			T40	1		T65	1		T66	1
all_pins[2]	transitions[0x0=>0x1]	103	1			T40	1		T65	1		T66	1
all_pins[2]	transitions[0x1=>0x0]	64	1			T49	1		T220	1		T221	4
all_pins[3]	values[0x0]	83687	1			T1	3		T2	4		T3	7
all_pins[3]	values[0x1]	86	1			T49	1		T220	3		T221	4
all_pins[3]	transitions[0x0=>0x1]	71	1			T49	1		T220	3		T221	2
all_pins[3]	transitions[0x1=>0x0]	50	1			T18	1		T225	3		T293	2
all_pins[4]	values[0x0]	83708	1			T1	3		T2	4		T3	7
all_pins[4]	values[0x1]	65	1			T18	1		T221	2		T224	1
all_pins[4]	transitions[0x0=>0x1]	46	1			T18	1		T221	2		T225	3
all_pins[4]	transitions[0x1=>0x0]	55	1			T221	1		T293	3		T286	2
all_pins[5]	values[0x0]	83699	1			T1	3		T2	4		T3	7
all_pins[5]	values[0x1]	74	1			T221	1		T224	1		T225	1
all_pins[5]	transitions[0x0=>0x1]	61	1			T224	1		T225	1		T293	4
all_pins[5]	transitions[0x1=>0x0]	103	1			T69	1		T70	1		T71	1
all_pins[6]	values[0x0]	83657	1			T1	3		T2	4		T3	7
all_pins[6]	values[0x1]	116	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x0=>0x1]	100	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x1=>0x0]	52	1			T53	1		T221	1		T222	1
all_pins[7]	values[0x0]	83705	1			T1	3		T2	4		T3	7
all_pins[7]	values[0x1]	68	1			T53	1		T221	1		T222	2
all_pins[7]	transitions[0x0=>0x1]	49	1			T53	1		T221	1		T222	2
all_pins[7]	transitions[0x1=>0x0]	72	1			T56	1		T58	1		T59	1
all_pins[8]	values[0x0]	83682	1			T1	3		T2	4		T3	7
all_pins[8]	values[0x1]	91	1			T56	1		T58	1		T59	1
all_pins[8]	transitions[0x0=>0x1]	76	1			T56	1		T58	1		T59	1
all_pins[8]	transitions[0x1=>0x0]	54	1			T3	2		T63	2		T64	2
all_pins[9]	values[0x0]	83704	1			T1	3		T2	4		T3	5
all_pins[9]	values[0x1]	69	1			T3	2		T63	2		T64	2
all_pins[9]	transitions[0x0=>0x1]	58	1			T3	2		T63	2		T64	2
all_pins[9]	transitions[0x1=>0x0]	55	1			T221	2		T225	2		T294	4
all_pins[10]	values[0x0]	83707	1			T1	3		T2	4		T3	7
all_pins[10]	values[0x1]	66	1			T221	2		T225	2		T293	1
all_pins[10]	transitions[0x0=>0x1]	48	1			T221	2		T293	1		T294	2
all_pins[10]	transitions[0x1=>0x0]	96	1			T73	1		T74	1		T75	1
all_pins[11]	values[0x0]	83659	1			T1	3		T2	4		T3	7
all_pins[11]	values[0x1]	114	1			T73	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	93	1			T73	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	47	1			T76	1		T77	1		T79	1
all_pins[12]	values[0x0]	83705	1			T1	3		T2	4		T3	7
all_pins[12]	values[0x1]	68	1			T76	1		T77	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	53	1			T76	1		T77	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	112	1			T1	1		T82	1		T83	1
all_pins[13]	values[0x0]	83646	1			T1	2		T2	4		T3	7
all_pins[13]	values[0x1]	127	1			T1	1		T82	1		T83	1
all_pins[13]	transitions[0x0=>0x1]	109	1			T1	1		T82	1		T83	1
all_pins[13]	transitions[0x1=>0x0]	41	1			T221	1		T224	4		T293	3
all_pins[14]	values[0x0]	83714	1			T1	3		T2	4		T3	7
all_pins[14]	values[0x1]	59	1			T221	1		T224	5		T293	3
all_pins[14]	transitions[0x0=>0x1]	37	1			T224	2		T293	3		T286	1
all_pins[14]	transitions[0x1=>0x0]	70	1			T220	1		T221	1		T222	3
all_pins[15]	values[0x0]	83681	1			T1	3		T2	4		T3	7
all_pins[15]	values[0x1]	92	1			T220	1		T221	2		T222	3
all_pins[15]	transitions[0x0=>0x1]	56	1			T220	1		T221	1		T222	3
all_pins[15]	transitions[0x1=>0x0]	41	1			T17	4		T20	4		T25	4
all_pins[16]	values[0x0]	83696	1			T1	3		T2	4		T3	7
all_pins[16]	values[0x1]	77	1			T17	4		T20	4		T25	4
all_pins[16]	transitions[0x0=>0x1]	55	1			T17	4		T20	4		T25	4
all_pins[16]	transitions[0x1=>0x0]	49	1			T29	1		T60	1		T61	1
all_pins[17]	values[0x0]	83702	1			T1	3		T2	4		T3	7
all_pins[17]	values[0x1]	71	1			T29	1		T60	1		T61	1
all_pins[17]	transitions[0x0=>0x1]	71	1			T29	1		T60	1		T61	1