Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4520	1			T67	58		T68	7		T605	16
invalid_ep[0xd]	4564	1			T67	68		T68	26		T605	10
invalid_ep[0xe]	4581	1			T67	81		T68	6		T605	13
invalid_ep[0xf]	4503	1			T67	65		T119	1		T68	13
endpoints[0x0]	17428	1			T1	1		T29	1		T41	3
endpoints[0x1]	11289	1			T30	1		T41	1		T32	2
endpoints[0x2]	12173	1			T32	2		T34	2		T50	3
endpoints[0x3]	12979	1			T42	1		T32	1		T34	2
endpoints[0x4]	12948	1			T41	7		T32	5		T34	2
endpoints[0x5]	14629	1			T41	3		T32	4		T34	2
endpoints[0x6]	12232	1			T32	2		T34	2		T160	2
endpoints[0x7]	11370	1			T32	1		T34	2		T22	2
endpoints[0x8]	13915	1			T32	2		T34	2		T37	8
endpoints[0x9]	12359	1			T2	1		T31	5		T41	15
endpoints[0xa]	13713	1			T41	2		T42	1		T32	1
endpoints[0xb]	14693	1			T32	2		T34	2		T36	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24019	1			T2	1		T29	1		T41	8
pkt_types[PidTypeOutToken]	75299	1			T1	1		T31	1		T41	5
pkt_types[PidTypeInToken]	61320	1			T30	1		T31	4		T41	9

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1037	1			T67	18		T120	12		T180	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	988	1			T67	17		T120	13		T180	16
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1063	1			T67	24		T120	23		T462	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	974	1			T67	16		T119	1		T120	17
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1661	1			T29	1		T54	1		T165	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1568	1			T41	1		T198	1		T159	2
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1596	1			T50	1		T4	2		T243	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1767	1			T168	1		T112	5		T161	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1729	1			T41	2		T48	1		T60	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1605	1			T51	1		T4	3		T67	9
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1675	1			T67	17		T170	5		T171	5
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1586	1			T67	26		T172	2		T120	12
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1693	1			T37	8		T163	1		T111	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1746	1			T2	1		T41	4		T243	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1625	1			T41	1		T33	9		T67	19
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1706	1			T87	1		T4	3		T176	9
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1526	1			T67	13		T68	7		T605	16
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1572	1			T67	18		T68	26		T605	10
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1538	1			T67	13		T68	6		T605	13
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1582	1			T67	20		T68	13		T605	11
pkt_types[PidTypeOutToken]	endpoints[0x0]	9869	1			T1	1		T34	1		T4	3
pkt_types[PidTypeOutToken]	endpoints[0x1]	4313	1			T32	1		T34	1		T456	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	4608	1			T32	1		T34	1		T50	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	4913	1			T34	1		T19	1		T24	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5728	1			T41	2		T32	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	7027	1			T41	1		T32	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	4674	1			T32	1		T34	1		T160	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4386	1			T32	1		T34	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5688	1			T32	2		T34	1		T166	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	4091	1			T31	1		T41	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	6531	1			T41	1		T32	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	7253	1			T32	2		T34	1		T36	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	978	1			T67	16		T120	18		T180	22
pkt_types[PidTypeInToken]	invalid_ep[0xd]	970	1			T67	18		T120	14		T462	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1021	1			T67	23		T120	11		T180	18
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1016	1			T67	19		T120	14		T180	11
pkt_types[PidTypeInToken]	endpoints[0x0]	4755	1			T41	1		T34	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0x1]	4284	1			T30	1		T32	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4834	1			T32	1		T34	1		T50	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5217	1			T42	1		T32	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4324	1			T41	2		T32	4		T34	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4948	1			T32	3		T34	1		T51	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4788	1			T32	1		T34	1		T160	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4308	1			T34	1		T22	1		T161	8
pkt_types[PidTypeInToken]	endpoints[0x8]	5381	1			T34	1		T163	1		T111	1
pkt_types[PidTypeInToken]	endpoints[0x9]	5374	1			T31	4		T41	6		T34	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4465	1			T34	1		T62	1		T69	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4657	1			T34	1		T36	1		T43	1