Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T220	4		T221	7		T222	4
all_values[1]	290	1			T220	4		T221	7		T222	4
all_values[2]	290	1			T220	4		T221	7		T222	4
all_values[3]	290	1			T220	4		T221	7		T222	4
all_values[4]	290	1			T220	4		T221	7		T222	4
all_values[5]	290	1			T220	4		T221	7		T222	4
all_values[6]	290	1			T220	4		T221	7		T222	4
all_values[7]	290	1			T220	4		T221	7		T222	4
all_values[8]	290	1			T220	4		T221	7		T222	4
all_values[9]	290	1			T220	4		T221	7		T222	4
all_values[10]	290	1			T220	4		T221	7		T222	4
all_values[11]	290	1			T220	4		T221	7		T222	4
all_values[12]	290	1			T220	4		T221	7		T222	4
all_values[13]	290	1			T220	4		T221	7		T222	4
all_values[14]	290	1			T220	4		T221	7		T222	4
all_values[15]	290	1			T220	4		T221	7		T222	4
all_values[16]	290	1			T220	4		T221	7		T222	4
all_values[17]	290	1			T220	4		T221	7		T222	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6776

1

T220

97

T221

162

T222

99

auto[1]

2504

1

T220

31

T221

62

T222

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6350

1

T220

86

T221

155

T222

91

auto[1]

2930

1

T220

42

T221

69

T222

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5433

1

T220

77

T221

133

T222

85

auto[1]

3847

1

T220

51

T221

91

T222

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	110	1			T220	2		T221	2		T224	4
all_values[0]	auto[0]	auto[1]	auto[0]	61	1			T220	1		T221	3		T222	1
all_values[0]	auto[1]	auto[0]	auto[1]	77	1			T220	1		T221	1		T222	2
all_values[0]	auto[1]	auto[1]	auto[1]	42	1			T221	1		T222	1		T225	1
all_values[1]	auto[0]	auto[0]	auto[0]	84	1			T220	2		T221	3		T224	5
all_values[1]	auto[0]	auto[1]	auto[0]	84	1			T220	1		T221	1		T222	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T220	1		T221	2		T222	2
all_values[1]	auto[1]	auto[1]	auto[1]	54	1			T221	1		T222	1		T293	5
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T220	1		T221	5		T222	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T221	1		T222	2		T224	2
all_values[2]	auto[0]	auto[1]	auto[0]	48	1			T293	1		T294	1		T286	2
all_values[2]	auto[0]	auto[1]	auto[1]	42	1			T220	2		T224	2		T294	2
all_values[2]	auto[1]	auto[0]	auto[1]	59	1			T221	1		T222	1		T224	2
all_values[2]	auto[1]	auto[1]	auto[1]	46	1			T220	1		T224	1		T294	1
all_values[3]	auto[0]	auto[0]	auto[0]	67	1			T220	1		T221	1		T222	2
all_values[3]	auto[0]	auto[0]	auto[1]	34	1			T294	2		T286	1		T295	1
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T221	1		T222	1		T296	1
all_values[3]	auto[0]	auto[1]	auto[1]	32	1			T220	1		T221	2		T224	3
all_values[3]	auto[1]	auto[0]	auto[1]	68	1			T224	1		T225	2		T293	3
all_values[3]	auto[1]	auto[1]	auto[1]	60	1			T220	2		T221	3		T222	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1			T221	2		T222	2		T224	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1			T220	1		T221	1		T224	2
all_values[4]	auto[0]	auto[1]	auto[0]	55	1			T220	1		T222	1		T296	1
all_values[4]	auto[0]	auto[1]	auto[1]	28	1			T221	1		T225	3		T293	1
all_values[4]	auto[1]	auto[0]	auto[1]	70	1			T220	2		T221	2		T224	2
all_values[4]	auto[1]	auto[1]	auto[1]	51	1			T221	1		T222	1		T224	1
all_values[5]	auto[0]	auto[0]	auto[0]	45	1			T220	2		T221	1		T225	2
all_values[5]	auto[0]	auto[0]	auto[1]	21	1			T220	1		T294	1		T297	2
all_values[5]	auto[0]	auto[1]	auto[0]	66	1			T221	2		T222	3		T224	3
all_values[5]	auto[0]	auto[1]	auto[1]	32	1			T293	3		T286	1		T296	2
all_values[5]	auto[1]	auto[0]	auto[1]	68	1			T220	1		T221	1		T222	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1			T221	3		T224	3		T225	1
all_values[6]	auto[0]	auto[0]	auto[0]	65	1			T222	2		T224	3		T225	1
all_values[6]	auto[0]	auto[0]	auto[1]	23	1			T221	1		T225	1		T293	1
all_values[6]	auto[0]	auto[1]	auto[0]	57	1			T221	1		T224	1		T293	1
all_values[6]	auto[0]	auto[1]	auto[1]	26	1			T220	1		T221	1		T222	1
all_values[6]	auto[1]	auto[0]	auto[1]	56	1			T220	1		T221	1		T222	1
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T220	2		T221	3		T224	2
all_values[7]	auto[0]	auto[0]	auto[0]	84	1			T220	1		T224	1		T225	2
all_values[7]	auto[0]	auto[1]	auto[0]	85	1			T220	1		T221	3		T222	2
all_values[7]	auto[1]	auto[0]	auto[1]	62	1			T220	2		T221	2		T222	1
all_values[7]	auto[1]	auto[1]	auto[1]	59	1			T221	2		T222	1		T224	2
all_values[8]	auto[0]	auto[0]	auto[0]	88	1			T220	1		T221	3		T222	3
all_values[8]	auto[0]	auto[1]	auto[0]	80	1			T221	2		T224	3		T225	2
all_values[8]	auto[1]	auto[0]	auto[1]	59	1			T220	2		T221	1		T222	1
all_values[8]	auto[1]	auto[1]	auto[1]	63	1			T220	1		T221	1		T224	2
all_values[9]	auto[0]	auto[0]	auto[0]	58	1			T221	1		T224	2		T225	1
all_values[9]	auto[0]	auto[0]	auto[1]	26	1			T221	2		T225	1		T293	1
all_values[9]	auto[0]	auto[1]	auto[0]	61	1			T220	2		T221	1		T222	1
all_values[9]	auto[0]	auto[1]	auto[1]	22	1			T220	1		T222	1		T296	1
all_values[9]	auto[1]	auto[0]	auto[1]	77	1			T221	3		T222	2		T224	2
all_values[9]	auto[1]	auto[1]	auto[1]	46	1			T220	1		T224	1		T225	1
all_values[10]	auto[0]	auto[0]	auto[0]	53	1			T221	3		T222	3		T293	2
all_values[10]	auto[0]	auto[0]	auto[1]	30	1			T220	3		T224	2		T293	2
all_values[10]	auto[0]	auto[1]	auto[0]	55	1			T222	1		T225	1		T294	1
all_values[10]	auto[0]	auto[1]	auto[1]	29	1			T221	1		T225	1		T294	1
all_values[10]	auto[1]	auto[0]	auto[1]	53	1			T220	1		T221	2		T224	1
all_values[10]	auto[1]	auto[1]	auto[1]	70	1			T221	1		T224	4		T225	1
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T221	1		T222	1		T224	1
all_values[11]	auto[0]	auto[0]	auto[1]	29	1			T222	1		T224	2		T293	2
all_values[11]	auto[0]	auto[1]	auto[0]	64	1			T220	2		T221	2		T224	1
all_values[11]	auto[0]	auto[1]	auto[1]	29	1			T220	1		T221	1		T225	1
all_values[11]	auto[1]	auto[0]	auto[1]	51	1			T221	1		T224	3		T293	1
all_values[11]	auto[1]	auto[1]	auto[1]	63	1			T220	1		T221	2		T222	2
all_values[12]	auto[0]	auto[0]	auto[0]	65	1			T220	2		T221	1		T222	2
all_values[12]	auto[0]	auto[0]	auto[1]	17	1			T221	1		T298	1		T299	1
all_values[12]	auto[0]	auto[1]	auto[0]	62	1			T220	2		T222	1		T224	3
all_values[12]	auto[0]	auto[1]	auto[1]	32	1			T221	1		T293	1		T294	1
all_values[12]	auto[1]	auto[0]	auto[1]	57	1			T221	3		T224	1		T294	4
all_values[12]	auto[1]	auto[1]	auto[1]	57	1			T221	1		T222	1		T224	1
all_values[13]	auto[0]	auto[0]	auto[0]	64	1			T220	2		T221	1		T225	4
all_values[13]	auto[0]	auto[0]	auto[1]	27	1			T224	1		T286	1		T300	1
all_values[13]	auto[0]	auto[1]	auto[0]	39	1			T220	2		T221	4		T222	1
all_values[13]	auto[0]	auto[1]	auto[1]	26	1			T224	1		T286	1		T296	1
all_values[13]	auto[1]	auto[0]	auto[1]	69	1			T221	1		T222	2		T224	3
all_values[13]	auto[1]	auto[1]	auto[1]	65	1			T221	1		T222	1		T224	1
all_values[14]	auto[0]	auto[0]	auto[0]	64	1			T221	1		T222	1		T224	1
all_values[14]	auto[0]	auto[0]	auto[1]	33	1			T220	1		T221	2		T293	1
all_values[14]	auto[0]	auto[1]	auto[0]	55	1			T221	1		T294	1		T286	1
all_values[14]	auto[0]	auto[1]	auto[1]	23	1			T224	3		T293	2		T286	2
all_values[14]	auto[1]	auto[0]	auto[1]	71	1			T220	3		T221	2		T222	1
all_values[14]	auto[1]	auto[1]	auto[1]	44	1			T221	1		T222	2		T224	2
all_values[15]	auto[0]	auto[0]	auto[0]	57	1			T224	2		T293	4		T296	2
all_values[15]	auto[0]	auto[0]	auto[1]	26	1			T220	1		T221	1		T225	2
all_values[15]	auto[0]	auto[1]	auto[0]	45	1			T221	2		T293	1		T294	1
all_values[15]	auto[0]	auto[1]	auto[1]	41	1			T222	1		T224	2		T294	3
all_values[15]	auto[1]	auto[0]	auto[1]	52	1			T220	1		T221	1		T222	2
all_values[15]	auto[1]	auto[1]	auto[1]	69	1			T220	2		T221	3		T222	1
all_values[16]	auto[0]	auto[0]	auto[0]	53	1			T221	1		T222	2		T225	3
all_values[16]	auto[0]	auto[0]	auto[1]	29	1			T221	1		T224	3		T293	1
all_values[16]	auto[0]	auto[1]	auto[0]	64	1			T220	1		T221	2		T222	1
all_values[16]	auto[0]	auto[1]	auto[1]	23	1			T220	2		T221	1		T224	1
all_values[16]	auto[1]	auto[0]	auto[1]	59	1			T220	1		T222	1		T224	1
all_values[16]	auto[1]	auto[1]	auto[1]	62	1			T221	2		T224	1		T293	1
all_values[17]	auto[0]	auto[0]	auto[0]	84	1			T220	3		T221	3		T222	2
all_values[17]	auto[0]	auto[1]	auto[0]	82	1			T221	3		T224	2		T225	2
all_values[17]	auto[1]	auto[0]	auto[1]	69	1			T220	1		T221	1		T222	2
all_values[17]	auto[1]	auto[1]	auto[1]	55	1			T224	1		T293	1		T294	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal