Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9028289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9617692

1

T1

5

T2

12

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18001998	1			T1	3		T2	7		T3	7
values[0x0]	321530	1			T1	3		T2	8		T3	5
values[0x1]	322453	1			T1	6		T2	7		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7175558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11470423

1

T1

8

T2

15

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51696	1			T31	2		T35	3		T50	1
valid_sources[0x01]	71207	1			T33	1		T35	1		T36	1
valid_sources[0x02]	82064	1			T45	1		T34	1		T36	1
valid_sources[0x03]	59728	1			T1	1		T43	7		T44	3
valid_sources[0x04]	70292	1			T7	4		T18	11		T4	25
valid_sources[0x05]	73655	1			T35	2		T51	1		T50	2
valid_sources[0x06]	86542	1			T31	1		T34	1		T66	52
valid_sources[0x07]	60807	1			T44	1		T34	3		T39	1
valid_sources[0x08]	53951	1			T31	3		T7	1		T18	4
valid_sources[0x09]	53244	1			T44	1		T51	1		T7	12
valid_sources[0x0a]	52091	1			T44	1		T51	1		T50	3
valid_sources[0x0b]	53627	1			T31	4		T44	1		T34	1
valid_sources[0x0c]	53549	1			T31	3		T44	1		T45	3
valid_sources[0x0d]	53473	1			T35	2		T18	9		T58	1
valid_sources[0x0e]	52303	1			T44	3		T35	1		T7	11
valid_sources[0x0f]	145123	1			T31	3		T34	2		T66	98
valid_sources[0x10]	71931	1			T3	1		T44	1		T93	1
valid_sources[0x11]	84255	1			T18	5		T21	1		T25	1
valid_sources[0x12]	53589	1			T93	1		T76	2		T18	6
valid_sources[0x13]	117989	1			T45	2		T34	1		T18	3
valid_sources[0x14]	140840	1			T1	1		T30	1		T78	3
valid_sources[0x15]	123439	1			T31	1		T34	3		T18	7
valid_sources[0x16]	53316	1			T30	1		T35	3		T39	1
valid_sources[0x17]	53881	1			T44	1		T7	10		T18	8
valid_sources[0x18]	120928	1			T44	1		T45	1		T92	1
valid_sources[0x19]	51660	1			T93	1		T76	2		T50	2
valid_sources[0x1a]	103610	1			T34	1		T76	3		T18	4
valid_sources[0x1b]	77864	1			T31	5		T92	3		T76	1
valid_sources[0x1c]	52864	1			T34	1		T18	7		T21	1
valid_sources[0x1d]	177625	1			T18	5		T19	1		T21	1
valid_sources[0x1e]	325346	1			T1	1		T44	1		T34	1
valid_sources[0x1f]	52735	1			T34	1		T35	1		T18	4
valid_sources[0x20]	166784	1			T34	1		T164	6		T18	6
valid_sources[0x21]	74051	1			T34	1		T90	1		T18	8
valid_sources[0x22]	71731	1			T34	2		T18	7		T25	1
valid_sources[0x23]	52421	1			T44	1		T34	1		T39	1
valid_sources[0x24]	125885	1			T31	10		T34	1		T35	12
valid_sources[0x25]	129161	1			T44	2		T35	3		T52	3
valid_sources[0x26]	188289	1			T31	5		T35	2		T92	1
valid_sources[0x27]	67372	1			T31	7		T34	1		T18	5
valid_sources[0x28]	53032	1			T2	3		T30	1		T31	3
valid_sources[0x29]	60772	1			T2	5		T35	1		T7	3
valid_sources[0x2a]	152789	1			T34	1		T39	1		T91	1
valid_sources[0x2b]	80791	1			T33	2		T34	1		T50	1
valid_sources[0x2c]	53155	1			T34	1		T7	15		T17	2
valid_sources[0x2d]	53580	1			T35	1		T18	3		T21	1
valid_sources[0x2e]	151057	1			T35	1		T18	5		T4	25
valid_sources[0x2f]	81999	1			T34	1		T18	5		T4	32
valid_sources[0x30]	160266	1			T34	4		T121	1		T54	1
valid_sources[0x31]	52766	1			T44	1		T34	2		T93	1
valid_sources[0x32]	76828	1			T34	1		T51	1		T52	2
valid_sources[0x33]	54663	1			T44	1		T34	2		T66	52
valid_sources[0x34]	55226	1			T1	1		T45	1		T34	1
valid_sources[0x35]	53621	1			T35	3		T18	7		T4	30
valid_sources[0x36]	80441	1			T34	2		T35	3		T39	1
valid_sources[0x37]	53852	1			T44	2		T34	1		T35	7
valid_sources[0x38]	58458	1			T34	2		T66	19		T91	1
valid_sources[0x39]	74116	1			T7	5		T18	3		T4	26
valid_sources[0x3a]	53245	1			T45	2		T34	1		T91	1
valid_sources[0x3b]	53087	1			T34	1		T91	3		T18	5
valid_sources[0x3c]	52756	1			T39	1		T52	1		T18	8
valid_sources[0x3d]	52502	1			T34	1		T35	2		T568	7
valid_sources[0x3e]	53083	1			T1	1		T31	5		T36	1
valid_sources[0x3f]	55418	1			T34	3		T35	3		T66	68
valid_sources[0x40]	53368	1			T34	1		T39	1		T219	2
valid_sources[0x41]	53200	1			T54	1		T18	9		T21	1
valid_sources[0x42]	53124	1			T31	2		T44	2		T35	1
valid_sources[0x43]	66203	1			T18	7		T23	2		T4	16
valid_sources[0x44]	52656	1			T44	1		T45	2		T76	2
valid_sources[0x45]	53608	1			T30	1		T31	5		T44	3
valid_sources[0x46]	52892	1			T91	1		T18	5		T19	1
valid_sources[0x47]	53759	1			T44	1		T92	3		T7	5
valid_sources[0x48]	84753	1			T34	1		T92	2		T18	3
valid_sources[0x49]	70208	1			T123	1		T18	10		T4	23
valid_sources[0x4a]	52668	1			T34	2		T18	8		T8	3
valid_sources[0x4b]	100350	1			T44	1		T45	2		T7	2
valid_sources[0x4c]	52889	1			T31	8		T35	5		T7	1
valid_sources[0x4d]	52766	1			T44	1		T123	1		T18	2
valid_sources[0x4e]	261030	1			T34	1		T35	3		T18	11
valid_sources[0x4f]	53844	1			T45	5		T18	5		T23	1
valid_sources[0x50]	53382	1			T1	1		T35	2		T7	5
valid_sources[0x51]	64174	1			T31	1		T34	3		T18	6
valid_sources[0x52]	68260	1			T34	2		T54	1		T7	8
valid_sources[0x53]	52633	1			T34	1		T66	57		T39	1
valid_sources[0x54]	52973	1			T44	1		T35	1		T39	1
valid_sources[0x55]	53337	1			T34	3		T35	5		T50	1
valid_sources[0x56]	80092	1			T78	2		T18	5		T58	1
valid_sources[0x57]	53143	1			T31	2		T35	4		T18	7
valid_sources[0x58]	52943	1			T34	2		T35	2		T18	8
valid_sources[0x59]	162482	1			T34	1		T35	4		T131	1
valid_sources[0x5a]	56472	1			T39	2		T29	1		T123	1
valid_sources[0x5b]	54260	1			T31	1		T44	1		T35	3
valid_sources[0x5c]	68519	1			T45	1		T34	1		T76	1
valid_sources[0x5d]	56601	1			T3	3		T34	2		T35	2
valid_sources[0x5e]	134188	1			T45	1		T34	1		T131	1
valid_sources[0x5f]	131876	1			T35	1		T76	1		T29	1
valid_sources[0x60]	101040	1			T44	1		T34	4		T76	1
valid_sources[0x61]	52053	1			T31	1		T44	1		T33	1
valid_sources[0x62]	52580	1			T31	1		T34	1		T39	1
valid_sources[0x63]	52850	1			T1	1		T34	1		T35	2
valid_sources[0x64]	53564	1			T30	2		T42	1		T34	1
valid_sources[0x65]	53989	1			T7	1		T18	7		T58	1
valid_sources[0x66]	150632	1			T34	1		T39	1		T18	6
valid_sources[0x67]	65560	1			T1	1		T35	1		T18	3
valid_sources[0x68]	99823	1			T42	1		T34	1		T18	8
valid_sources[0x69]	52906	1			T32	1		T35	1		T90	2
valid_sources[0x6a]	127173	1			T1	1		T34	3		T18	9
valid_sources[0x6b]	54194	1			T32	10		T18	5		T21	1
valid_sources[0x6c]	52536	1			T34	1		T18	6		T21	1
valid_sources[0x6d]	53318	1			T32	2		T34	1		T35	3
valid_sources[0x6e]	153016	1			T30	1		T34	1		T39	1
valid_sources[0x6f]	134936	1			T2	14		T31	8		T36	13
valid_sources[0x70]	52750	1			T50	1		T54	1		T18	5
valid_sources[0x71]	52833	1			T91	1		T18	11		T21	1
valid_sources[0x72]	52934	1			T45	1		T34	1		T50	1
valid_sources[0x73]	56709	1			T34	3		T39	1		T18	6
valid_sources[0x74]	52406	1			T7	6		T18	6		T4	32
valid_sources[0x75]	56865	1			T45	2		T34	2		T39	1
valid_sources[0x76]	54945	1			T39	2		T18	6		T4	30
valid_sources[0x77]	54660	1			T39	1		T51	1		T18	8
valid_sources[0x78]	114935	1			T34	1		T40	2		T18	8
valid_sources[0x79]	72868	1			T91	1		T131	1		T18	6
valid_sources[0x7a]	119867	1			T35	1		T131	1		T18	4
valid_sources[0x7b]	63803	1			T31	1		T34	2		T17	1
valid_sources[0x7c]	67459	1			T42	1		T34	2		T91	3
valid_sources[0x7d]	71264	1			T39	1		T40	1		T18	6
valid_sources[0x7e]	108724	1			T35	4		T7	6		T18	8
valid_sources[0x7f]	61017	1			T33	3		T34	1		T18	3
valid_sources[0x80]	88303	1			T34	1		T7	14		T18	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9097829

1

T1

1

T2

3

T3

4

values[0x0]

all_enables

biggest_size

268692

1

T1

1

T2

6

T3

2

values[0x1]

all_enables

biggest_size

251171

1

T1

3

T2

3

T30

3