Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	581686887	9950	0	0
ep_in_enable_rd_A	581686887	1740	0	0
ep_out_enable_rd_A	581686887	1611	0	0
in_iso_rd_A	581686887	1506	0	0
intr_enable_rd_A	581686887	2583	0	0
out_iso_rd_A	581686887	1709	0	0
phy_config_rd_A	581686887	1113	0	0
phy_pins_drive_rd_A	581686887	1539	0	0
rxenable_setup_rd_A	581686887	1715	0	0
set_nak_out_rd_A	581686887	1807	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	9950	0	0
T201	4765	11	0	0
T202	11742	713	0	0
T203	29899	3	0	0
T236	7376	465	0	0
T241	35184	4	0	0
T242	7739	358	0	0
T246	33340	4	0	0
T247	3891	13	0	0
T250	4670	597	0	0
T256	5867	21	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1740	0	0
T201	4765	5	0	0
T203	29899	244	0	0
T212	8651	8	0	0
T268	31167	164	0	0
T269	3047	21	0	0
T282	5955	97	0	0
T285	10177	115	0	0
T286	9523	43	0	0
T287	10789	29	0	0
T288	4237	32	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1611	0	0
T201	4765	3	0	0
T203	29899	252	0	0
T268	31167	79	0	0
T269	3047	36	0	0
T282	5955	66	0	0
T285	10177	112	0	0
T286	9523	54	0	0
T287	10789	21	0	0
T288	4237	1	0	0
T289	6353	17	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1506	0	0
T201	4765	64	0	0
T203	29899	154	0	0
T212	8651	5	0	0
T268	31167	126	0	0
T269	3047	2	0	0
T282	5955	62	0	0
T285	10177	119	0	0
T286	9523	36	0	0
T287	10789	10	0	0
T288	4237	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	2583	0	0
T201	4765	73	0	0
T203	29899	382	0	0
T210	2957	11	0	0
T268	31167	120	0	0
T269	3047	1	0	0
T282	5955	85	0	0
T285	10177	100	0	0
T286	9523	57	0	0
T287	10789	23	0	0
T290	3645	19	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1709	0	0
T201	4765	58	0	0
T203	29899	254	0	0
T212	8651	3	0	0
T268	31167	103	0	0
T269	3047	1	0	0
T282	5955	3	0	0
T285	10177	106	0	0
T286	9523	54	0	0
T287	10789	30	0	0
T289	6353	22	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1113	0	0
T201	4765	35	0	0
T203	29899	80	0	0
T268	31167	137	0	0
T282	5955	45	0	0
T285	10177	119	0	0
T286	9523	62	0	0
T287	10789	18	0	0
T288	4237	2	0	0
T289	6353	11	0	0
T291	5099	36	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1539	0	0
T201	4765	37	0	0
T203	29899	105	0	0
T212	8651	7	0	0
T268	31167	116	0	0
T269	3047	3	0	0
T282	5955	87	0	0
T285	10177	96	0	0
T286	9523	51	0	0
T287	10789	20	0	0
T288	4237	21	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1715	0	0
T201	4765	7	0	0
T203	29899	180	0	0
T212	8651	2	0	0
T268	31167	136	0	0
T269	3047	34	0	0
T282	5955	56	0	0
T285	10177	106	0	0
T286	9523	66	0	0
T287	10789	14	0	0
T288	4237	56	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581686887	1807	0	0
T201	4765	1	0	0
T203	29899	181	0	0
T212	8651	8	0	0
T268	31167	116	0	0
T269	3047	15	0	0
T282	5955	85	0	0
T285	10177	126	0	0
T286	9523	64	0	0
T287	10789	1	0	0
T288	4237	36	0	0