Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81770	1			T1	2		T2	6		T3	4
all_values[1]	81770	1			T1	2		T2	6		T3	4
all_values[2]	81770	1			T1	2		T2	6		T3	4
all_values[3]	81770	1			T1	2		T2	6		T3	4
all_values[4]	81770	1			T1	2		T2	6		T3	4
all_values[5]	81770	1			T1	2		T2	6		T3	4
all_values[6]	81770	1			T1	2		T2	6		T3	4
all_values[7]	81770	1			T1	2		T2	6		T3	4
all_values[8]	81770	1			T1	2		T2	6		T3	4
all_values[9]	81770	1			T1	2		T2	6		T3	4
all_values[10]	81770	1			T1	2		T2	6		T3	4
all_values[11]	81770	1			T1	2		T2	6		T3	4
all_values[12]	81770	1			T1	2		T2	6		T3	4
all_values[13]	81770	1			T1	2		T2	6		T3	4
all_values[14]	81770	1			T1	2		T2	6		T3	4
all_values[15]	81770	1			T1	2		T2	6		T3	4
all_values[16]	81770	1			T1	2		T2	6		T3	4
all_values[17]	81770	1			T1	2		T2	6		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2606872

1

T1

64

T2

189

T3

128

auto[1]

9768

1

T2

3

T39

5

T40

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2171449

1

T1

57

T2

177

T3

110

auto[1]

445191

1

T1

7

T2

15

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	52924	1			T1	2		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	25504	1			T2	3		T3	1		T28	2
all_values[0]	auto[1]	auto[0]	3227	1			T48	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	115	1			T22	1		T408	1		T409	1
all_values[1]	auto[0]	auto[0]	77248	1			T1	2		T2	6		T3	4
all_values[1]	auto[0]	auto[1]	3081	1			T30	1		T37	2		T38	3
all_values[1]	auto[1]	auto[0]	539	1			T32	2		T34	2		T24	2
all_values[1]	auto[1]	auto[1]	902	1			T32	1		T34	12		T24	1
all_values[2]	auto[0]	auto[0]	4407	1			T1	1		T2	5		T3	1
all_values[2]	auto[0]	auto[1]	77115	1			T1	1		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	133	1			T40	1		T68	1		T69	1
all_values[2]	auto[1]	auto[1]	115	1			T40	1		T68	1		T69	1
all_values[3]	auto[0]	auto[0]	79825	1			T1	2		T2	6		T3	4
all_values[3]	auto[0]	auto[1]	321	1			T18	1		T70	1		T71	1
all_values[3]	auto[1]	auto[0]	1574	1			T18	1484		T215	3		T306	1
all_values[3]	auto[1]	auto[1]	50	1			T18	1		T215	1		T218	2
all_values[4]	auto[0]	auto[0]	4380	1			T1	1		T2	5		T3	1
all_values[4]	auto[0]	auto[1]	77214	1			T1	1		T2	1		T3	3
all_values[4]	auto[1]	auto[0]	103	1			T49	1		T215	5		T219	2
all_values[4]	auto[1]	auto[1]	73	1			T49	1		T215	1		T307	2
all_values[5]	auto[0]	auto[0]	81263	1			T1	2		T2	6		T3	4
all_values[5]	auto[0]	auto[1]	366	1			T63	1		T7	1		T64	1
all_values[5]	auto[1]	auto[0]	96	1			T219	3		T218	4		T217	2
all_values[5]	auto[1]	auto[1]	45	1			T215	2		T217	4		T310	2
all_values[6]	auto[0]	auto[0]	81334	1			T1	2		T2	6		T3	4
all_values[6]	auto[0]	auto[1]	201	1			T70	1		T9	1		T97	1
all_values[6]	auto[1]	auto[0]	111	1			T215	1		T219	4		T218	3
all_values[6]	auto[1]	auto[1]	124	1			T64	1		T72	1		T73	1
all_values[7]	auto[0]	auto[0]	25210	1			T40	2		T42	3		T43	2
all_values[7]	auto[0]	auto[1]	56373	1			T1	2		T2	6		T3	4
all_values[7]	auto[1]	auto[0]	127	1			T52	2		T53	2		T54	2
all_values[7]	auto[1]	auto[1]	60	1			T52	1		T53	1		T54	1
all_values[8]	auto[0]	auto[0]	80839	1			T1	2		T2	6		T3	4
all_values[8]	auto[0]	auto[1]	234	1			T33	2		T191	2		T376	2
all_values[8]	auto[1]	auto[0]	606	1			T57	10		T58	10		T59	10
all_values[8]	auto[1]	auto[1]	91	1			T59	1		T60	1		T61	1
all_values[9]	auto[0]	auto[0]	81527	1			T1	2		T2	6		T3	4
all_values[9]	auto[0]	auto[1]	59	1			T215	2		T219	2		T217	2
all_values[9]	auto[1]	auto[0]	103	1			T39	3		T66	3		T67	3
all_values[9]	auto[1]	auto[1]	81	1			T39	2		T66	2		T67	2
all_values[10]	auto[0]	auto[0]	81228	1			T1	2		T2	6		T3	4
all_values[10]	auto[0]	auto[1]	386	1			T35	2		T37	1		T65	3
all_values[10]	auto[1]	auto[0]	97	1			T215	1		T219	3		T218	3
all_values[10]	auto[1]	auto[1]	59	1			T215	3		T219	2		T218	2
all_values[11]	auto[0]	auto[0]	80812	1			T1	2		T2	6		T3	4
all_values[11]	auto[0]	auto[1]	714	1			T42	1		T29	4		T36	4
all_values[11]	auto[1]	auto[0]	127	1			T76	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	117	1			T76	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	81398	1			T1	2		T2	6		T3	4
all_values[12]	auto[0]	auto[1]	198	1			T81	1		T83	1		T84	1
all_values[12]	auto[1]	auto[0]	97	1			T79	2		T80	2		T82	2
all_values[12]	auto[1]	auto[1]	77	1			T79	1		T80	1		T82	1
all_values[13]	auto[0]	auto[0]	81440	1			T1	2		T2	6		T3	4
all_values[13]	auto[0]	auto[1]	67	1			T81	1		T83	1		T84	1
all_values[13]	auto[1]	auto[0]	140	1			T42	1		T85	1		T86	1
all_values[13]	auto[1]	auto[1]	123	1			T42	1		T85	1		T86	1
all_values[14]	auto[0]	auto[0]	16121	1			T1	2		T2	6		T3	4
all_values[14]	auto[0]	auto[1]	65476	1			T40	1		T18	1486		T20	1
all_values[14]	auto[1]	auto[0]	97	1			T215	3		T219	1		T218	1
all_values[14]	auto[1]	auto[1]	76	1			T215	1		T219	3		T218	1
all_values[15]	auto[0]	auto[0]	4449	1			T1	1		T2	5		T3	1
all_values[15]	auto[0]	auto[1]	77185	1			T1	1		T2	1		T3	3
all_values[15]	auto[1]	auto[0]	89	1			T215	2		T219	4		T217	3
all_values[15]	auto[1]	auto[1]	47	1			T215	4		T217	1		T308	1
all_values[16]	auto[0]	auto[0]	80706	1			T1	2		T2	6		T3	4
all_values[16]	auto[0]	auto[1]	883	1			T28	1		T37	1		T75	1
all_values[16]	auto[1]	auto[0]	109	1			T29	4		T36	4		T74	4
all_values[16]	auto[1]	auto[1]	72	1			T29	4		T36	4		T74	4
all_values[17]	auto[0]	auto[0]	24073	1			T2	1		T39	5		T28	2
all_values[17]	auto[0]	auto[1]	57531	1			T1	2		T2	2		T3	4
all_values[17]	auto[1]	auto[0]	110	1			T2	2		T62	2		T215	1
all_values[17]	auto[1]	auto[1]	56	1			T2	1		T62	1		T215	1