Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 98.21 96.12 97.44 94.92 98.38 98.21 98.55


Total tests in report: 3901
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.43 60.43 78.52 78.52 58.40 58.40 78.89 78.89 32.20 32.20 72.17 72.17 90.67 90.67 12.13 12.13 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.905611708
69.17 8.75 82.38 3.86 68.46 10.06 81.24 2.35 50.85 18.64 78.91 6.74 91.07 0.40 31.31 19.19 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3776405813
74.37 5.20 90.89 8.52 77.85 9.40 83.16 1.92 50.85 0.00 90.43 11.52 91.47 0.40 35.93 4.62 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2587577911
77.93 3.56 92.64 1.75 80.76 2.90 87.63 4.48 61.02 10.17 91.89 1.46 93.45 1.98 38.10 2.17 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2916818544
80.25 2.32 92.97 0.32 83.42 2.66 87.85 0.21 67.80 6.78 92.64 0.75 93.45 0.00 43.62 5.52 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.3249489062
82.43 2.18 93.67 0.70 83.54 0.12 89.98 2.13 67.80 0.00 92.64 0.00 93.65 0.20 55.75 12.13 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.4213449993
83.67 1.23 95.11 1.44 86.49 2.95 90.41 0.43 67.80 0.00 95.55 2.91 93.65 0.00 56.65 0.90 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2286179585
84.63 0.96 95.87 0.76 87.61 1.12 91.26 0.85 67.80 0.00 95.59 0.04 94.64 0.99 59.64 2.99 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.1088784812
85.59 0.96 95.95 0.08 89.37 1.76 91.26 0.00 67.80 0.00 95.67 0.08 94.64 0.00 64.43 4.80 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2547389797
86.47 0.89 96.08 0.13 89.46 0.10 91.79 0.53 72.88 5.08 95.76 0.08 94.64 0.00 64.71 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3807642962
87.34 0.86 96.25 0.17 89.63 0.17 91.79 0.00 77.97 5.08 95.92 0.17 94.64 0.00 65.16 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.2450192079
87.98 0.64 96.27 0.02 89.70 0.07 95.42 3.62 77.97 0.00 95.97 0.04 94.84 0.20 65.70 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2224198806
88.58 0.60 96.33 0.06 89.80 0.10 95.63 0.21 81.36 3.39 96.05 0.08 94.84 0.00 66.06 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/7.usbdev_link_resume.889928561
89.13 0.55 96.50 0.17 89.89 0.10 95.63 0.00 84.75 3.39 96.21 0.17 94.84 0.00 66.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1285850026
89.62 0.49 96.86 0.36 90.18 0.29 95.63 0.00 84.75 0.00 96.26 0.04 96.43 1.59 67.24 1.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.4138953095
90.10 0.48 96.86 0.00 90.18 0.00 95.63 0.00 88.14 3.39 96.26 0.00 96.43 0.00 67.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/277.usbdev_tx_rx_disruption.1986514914
90.56 0.45 96.86 0.00 90.18 0.00 95.63 0.00 88.14 0.00 96.26 0.00 96.43 0.00 70.41 3.17 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.3618223695
91.00 0.44 97.60 0.74 91.37 1.19 95.63 0.00 88.14 0.00 97.42 1.16 96.43 0.00 70.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.1127081074
91.36 0.36 97.60 0.00 91.44 0.07 95.95 0.32 89.83 1.69 97.42 0.00 96.43 0.00 70.86 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.338054400
91.70 0.34 97.66 0.06 92.67 1.24 95.95 0.00 89.83 0.00 97.50 0.08 96.63 0.20 71.67 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.835109122
91.99 0.28 97.70 0.04 92.86 0.19 95.95 0.00 89.83 0.00 97.55 0.04 96.63 0.00 73.39 1.72 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.2846709902
92.26 0.27 97.70 0.00 92.86 0.00 96.16 0.21 91.53 1.69 97.55 0.00 96.63 0.00 73.39 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.1608155757
92.52 0.26 97.98 0.29 93.53 0.67 96.16 0.00 91.53 0.00 98.09 0.54 96.63 0.00 73.76 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.837024789
92.78 0.26 97.98 0.00 93.70 0.17 96.16 0.00 91.53 0.00 98.09 0.00 96.63 0.00 75.38 1.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.2539769907
93.03 0.25 98.00 0.02 93.70 0.00 96.16 0.00 93.22 1.69 98.13 0.04 96.63 0.00 75.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_disconnect.2891935607
93.27 0.24 98.00 0.00 93.70 0.00 96.16 0.00 94.92 1.69 98.13 0.00 96.63 0.00 75.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/295.usbdev_tx_rx_disruption.311811350
93.45 0.17 98.00 0.00 93.70 0.00 96.38 0.21 94.92 0.00 98.13 0.00 97.62 0.99 75.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3332207924
93.59 0.14 98.00 0.00 93.77 0.07 96.38 0.00 94.92 0.00 98.13 0.00 97.62 0.00 76.29 0.90 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/9.usbdev_device_address.3171532776
93.72 0.14 98.00 0.00 93.93 0.17 96.59 0.21 94.92 0.00 98.17 0.04 97.62 0.00 76.83 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_rx_full.169529991
93.85 0.13 98.00 0.00 94.01 0.07 96.80 0.21 94.92 0.00 98.17 0.00 97.62 0.00 77.47 0.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.790104532
93.97 0.12 98.00 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.17 0.00 97.62 0.00 78.28 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.2347258020
94.09 0.12 98.00 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.17 0.00 97.62 0.00 79.10 0.81 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.829797609
94.19 0.10 98.00 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.17 0.00 97.62 0.00 79.82 0.72 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.3203078683
94.29 0.10 98.00 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.17 0.00 97.62 0.00 80.54 0.72 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.1270501472
94.40 0.10 98.00 0.00 94.05 0.05 97.01 0.21 94.92 0.00 98.17 0.00 97.62 0.00 81.00 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1723166063
94.49 0.09 98.00 0.00 94.08 0.02 97.01 0.00 94.92 0.00 98.17 0.00 97.62 0.00 81.63 0.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.2925327664
94.58 0.09 98.00 0.00 94.08 0.00 97.01 0.00 94.92 0.00 98.17 0.00 97.62 0.00 82.26 0.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.3933472727
94.67 0.09 98.00 0.00 94.08 0.00 97.01 0.00 94.92 0.00 98.17 0.00 97.62 0.00 82.90 0.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/172.usbdev_endpoint_types.3434380718
94.76 0.09 98.00 0.00 94.08 0.00 97.01 0.00 94.92 0.00 98.17 0.00 97.62 0.00 83.53 0.63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/180.usbdev_endpoint_types.1041498720
94.85 0.09 98.00 0.00 94.12 0.05 97.23 0.21 94.92 0.00 98.17 0.00 97.62 0.00 83.89 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2378437055
94.93 0.08 98.00 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.17 0.00 97.62 0.00 84.43 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.1138720865
95.01 0.08 98.00 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.17 0.00 97.62 0.00 84.98 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/189.usbdev_endpoint_types.897377862
95.08 0.08 98.00 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.17 0.00 97.62 0.00 85.52 0.54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_types.1720335340
95.16 0.07 98.00 0.00 94.27 0.14 97.23 0.00 94.92 0.00 98.17 0.00 97.62 0.00 85.88 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.2646661940
95.22 0.07 98.04 0.04 94.29 0.02 97.23 0.00 94.92 0.00 98.21 0.04 97.62 0.00 86.24 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.2871041055
95.29 0.06 98.04 0.00 94.29 0.00 97.23 0.00 94.92 0.00 98.21 0.00 97.62 0.00 86.70 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/179.usbdev_endpoint_types.1973383068
95.35 0.06 98.04 0.00 94.29 0.00 97.23 0.00 94.92 0.00 98.21 0.00 97.62 0.00 87.15 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.3533098836
95.41 0.06 98.04 0.00 94.29 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.02 0.40 87.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.4086848308
95.46 0.06 98.04 0.00 94.48 0.19 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.20 87.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_resets.4164426842
95.51 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 87.51 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/146.usbdev_endpoint_types.2160832428
95.57 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 87.87 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/166.usbdev_endpoint_types.3786694446
95.62 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.24 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_restore.3140317486
95.67 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.60 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.868289428
95.72 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.96 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.1222094343
95.77 0.05 98.04 0.00 94.48 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.32 0.36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.1034128640
95.82 0.05 98.10 0.06 94.51 0.02 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.59 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/5.usbdev_nak_trans.751458925
95.87 0.05 98.16 0.06 94.58 0.07 97.44 0.21 94.92 0.00 98.21 0.00 98.21 0.00 89.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3243721873
95.91 0.04 98.16 0.00 94.58 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.86 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.3577686357
95.95 0.04 98.16 0.00 94.58 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.14 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.732394203
95.99 0.04 98.16 0.00 94.58 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.41 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/128.usbdev_endpoint_types.3727362666
96.03 0.04 98.16 0.00 94.58 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.68 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.129080923
96.07 0.04 98.16 0.00 94.58 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.95 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.760360388
96.10 0.03 98.16 0.00 94.79 0.21 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.95 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.593609388
96.13 0.03 98.16 0.00 94.81 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.13 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2178377610
96.16 0.03 98.16 0.00 94.84 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.31 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/165.usbdev_endpoint_types.3673418144
96.18 0.03 98.16 0.00 95.03 0.19 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.31 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2538155685
96.21 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.49 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.3779688448
96.23 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.67 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2724550721
96.26 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.86 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.1436359292
96.29 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.04 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/137.usbdev_endpoint_types.3401099386
96.31 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.22 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.627941965
96.34 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.40 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_types.3492515680
96.36 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/178.usbdev_endpoint_types.1009904243
96.39 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_types.1372605365
96.42 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 92.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_types.1371101344
96.44 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 93.12 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.1658956084
96.47 0.03 98.16 0.00 95.03 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 93.30 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.1177197251
96.49 0.02 98.17 0.02 95.05 0.02 97.44 0.00 94.92 0.00 98.25 0.04 98.21 0.00 93.39 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.2652438393
96.51 0.02 98.17 0.00 95.10 0.05 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 93.48 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.2893025945
96.53 0.02 98.17 0.00 95.15 0.05 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 93.57 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.4255993549
96.55 0.01 98.17 0.00 95.24 0.10 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 93.57 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/14.usbdev_phy_pins_sense.1731468077
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97.40 0.01 98.21 0.00 96.08 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/21.usbdev_nak_trans.2353277404
97.40 0.01 98.21 0.00 96.10 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/25.usbdev_nak_trans.4097580692
97.41 0.01 98.21 0.00 96.12 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/36.usbdev_nak_trans.2216519800

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.943175897
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3045427691
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2885901145
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.726538739
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.3955238256
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.710766568
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3446359392
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.2601564947
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3100868224
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.4164759348
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.149286776
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.692516197
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1576140590
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.1113064831
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1823982537
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1466737624
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4133001785
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1819453521
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.1871752435
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.389473602
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1401204350
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.854205438
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.3072713357
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.903104673
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.2846626820
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.1811507049
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.560544548
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.979596027
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.3717337833
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2465089379
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.1432972943
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1623381403
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1544478614
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.1700182812
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.548236215
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2747437748
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.2953185177
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3203350409
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.925752261
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3993085421
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1167030897
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.1325557959
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.209616793
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1213469013
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.1845540987
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.1471809703
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2047779058
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.2019897364
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.1758379699
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.475261811
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.196978693
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.2603265358
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1160231109
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.388802613
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2588074000
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.3422994515
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.908896768
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3457796967
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.1395935102
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.2761267210
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1035353407
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.4154998407
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.3351711698
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1014273885
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.2819834008
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.1719163541
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.573984547
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1738272067
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.2905022071
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1590804485
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.4220731629
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.3136365354
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.85541615
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.346664766
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.44700388
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1484862136
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.3270752140
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.588304175
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.1280469097
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3630921130
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.740327032
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.637675622
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.3217904379
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.3877718137
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.3918358876
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.389541940
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.1330330953
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.436030418
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.308231735
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.4111303199
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.3430582298
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.1458571749
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.2761002930
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1032160929
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.420336718
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3683074638
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.69206894
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.1403792432
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.3549042824
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.3423846777
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4280194473
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.290865118
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.3938997677
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.4138468588
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.420430614
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.2549892893
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.1554066483
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.1688667508
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.1623789174
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.3785462223
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.2281690240
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.788906683
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.3406512823
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.1122351324
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3758871410
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3950406665
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.414094441
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.3340823950
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.179209268
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.2569130122
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2756237895
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.2946538163
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3162349472
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.349883055
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.2291587412
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.363804466
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.2575302871
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.1215143305
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.2537131974
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.3226178923
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.3491289227
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.3912082951
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.536435275
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1907935837
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.2172429353
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.918070741
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1650401140
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.289705938
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.1527685524
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2823795113
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Total test records in report: 3901
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.905611708 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:05 AM UTC 24 192453889 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.2539082214 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:06 AM UTC 24 148158770 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.1953027059 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:06 AM UTC 24 156820983 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2538155685 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:06 AM UTC 24 153756235 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.338054400 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:07 AM UTC 24 172480575 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_enable.2327002838 Sep 24 08:54:04 AM UTC 24 Sep 24 08:54:07 AM UTC 24 77970900 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1723166063 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:07 AM UTC 24 213342996 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.837024789 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:07 AM UTC 24 253704449 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2587577911 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:07 AM UTC 24 570904576 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1709012883 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:08 AM UTC 24 496033605 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.1477339241 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:08 AM UTC 24 288180116 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.4169550547 Sep 24 08:54:06 AM UTC 24 Sep 24 08:54:08 AM UTC 24 176633611 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.879378729 Sep 24 08:54:06 AM UTC 24 Sep 24 08:54:08 AM UTC 24 203118127 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2274041751 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:09 AM UTC 24 351889409 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2286179585 Sep 24 08:54:04 AM UTC 24 Sep 24 08:54:09 AM UTC 24 903186102 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.1314178811 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:10 AM UTC 24 267193018 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.2289266827 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:10 AM UTC 24 182570107 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.3658335724 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:11 AM UTC 24 772154425 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.3867421322 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:11 AM UTC 24 453585860 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3776405813 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:11 AM UTC 24 1138619316 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.3917109169 Sep 24 08:54:09 AM UTC 24 Sep 24 08:54:12 AM UTC 24 234853128 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.1953432588 Sep 24 08:54:09 AM UTC 24 Sep 24 08:54:12 AM UTC 24 191251233 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.1815880736 Sep 24 08:54:10 AM UTC 24 Sep 24 08:54:13 AM UTC 24 157799467 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.1605705715 Sep 24 08:54:10 AM UTC 24 Sep 24 08:54:13 AM UTC 24 169855099 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.2844972277 Sep 24 08:54:11 AM UTC 24 Sep 24 08:54:13 AM UTC 24 227010474 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.917317394 Sep 24 08:54:11 AM UTC 24 Sep 24 08:54:14 AM UTC 24 192471878 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.390284023 Sep 24 08:54:11 AM UTC 24 Sep 24 08:54:15 AM UTC 24 496121083 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.2137060151 Sep 24 08:54:12 AM UTC 24 Sep 24 08:54:15 AM UTC 24 164784749 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.666138091 Sep 24 08:54:12 AM UTC 24 Sep 24 08:54:15 AM UTC 24 200867813 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1392100273 Sep 24 08:54:14 AM UTC 24 Sep 24 08:54:16 AM UTC 24 188035734 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.3530205156 Sep 24 08:54:14 AM UTC 24 Sep 24 08:54:16 AM UTC 24 157334318 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.2621582310 Sep 24 08:54:14 AM UTC 24 Sep 24 08:54:17 AM UTC 24 233069138 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.2051238349 Sep 24 08:54:14 AM UTC 24 Sep 24 08:54:17 AM UTC 24 210498619 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.2253260297 Sep 24 08:54:15 AM UTC 24 Sep 24 08:54:18 AM UTC 24 258558395 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.3320151292 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:18 AM UTC 24 4792237513 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3807642962 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:18 AM UTC 24 4747048380 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1285850026 Sep 24 08:54:15 AM UTC 24 Sep 24 08:54:18 AM UTC 24 306423511 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.2893025945 Sep 24 08:54:05 AM UTC 24 Sep 24 08:54:19 AM UTC 24 4199767952 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.1127081074 Sep 24 08:54:16 AM UTC 24 Sep 24 08:54:19 AM UTC 24 50255434 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.1468212460 Sep 24 08:54:16 AM UTC 24 Sep 24 08:54:19 AM UTC 24 162864133 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2884843349 Sep 24 08:54:16 AM UTC 24 Sep 24 08:54:19 AM UTC 24 259185444 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2378437055 Sep 24 08:54:17 AM UTC 24 Sep 24 08:54:20 AM UTC 24 181426447 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.1622843483 Sep 24 08:54:17 AM UTC 24 Sep 24 08:54:20 AM UTC 24 265646761 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.2924001386 Sep 24 08:54:17 AM UTC 24 Sep 24 08:54:20 AM UTC 24 199257743 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.2441145592 Sep 24 08:54:18 AM UTC 24 Sep 24 08:54:21 AM UTC 24 206279806 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.3210463788 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:22 AM UTC 24 6831007302 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.790104532 Sep 24 08:54:20 AM UTC 24 Sep 24 08:54:23 AM UTC 24 142722401 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.580739338 Sep 24 08:54:20 AM UTC 24 Sep 24 08:54:23 AM UTC 24 193077383 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.1342581105 Sep 24 08:54:20 AM UTC 24 Sep 24 08:54:23 AM UTC 24 349387776 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.2858878574 Sep 24 08:54:21 AM UTC 24 Sep 24 08:54:24 AM UTC 24 176483048 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.3255884794 Sep 24 08:54:21 AM UTC 24 Sep 24 08:54:24 AM UTC 24 309029287 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.3110621862 Sep 24 08:54:22 AM UTC 24 Sep 24 08:54:25 AM UTC 24 196134562 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.732394203 Sep 24 08:54:21 AM UTC 24 Sep 24 08:54:25 AM UTC 24 414264063 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.863868680 Sep 24 08:54:22 AM UTC 24 Sep 24 08:54:26 AM UTC 24 249978866 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.3486206745 Sep 24 08:54:24 AM UTC 24 Sep 24 08:54:26 AM UTC 24 162757861 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.3011541943 Sep 24 08:54:25 AM UTC 24 Sep 24 08:54:27 AM UTC 24 151084446 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.1784407989 Sep 24 08:54:27 AM UTC 24 Sep 24 08:54:31 AM UTC 24 506361769 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.4247276595 Sep 24 08:54:26 AM UTC 24 Sep 24 08:54:31 AM UTC 24 856426415 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3243721873 Sep 24 08:54:29 AM UTC 24 Sep 24 08:54:32 AM UTC 24 39732435 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3572258513 Sep 24 08:54:10 AM UTC 24 Sep 24 08:54:32 AM UTC 24 2207672628 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2224198806 Sep 24 08:54:28 AM UTC 24 Sep 24 08:54:33 AM UTC 24 657172478 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.3348575139 Sep 24 08:54:09 AM UTC 24 Sep 24 08:54:33 AM UTC 24 1652349234 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2916818544 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:35 AM UTC 24 21274132193 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.1091147666 Sep 24 08:54:33 AM UTC 24 Sep 24 08:54:35 AM UTC 24 151243863 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.1435090910 Sep 24 08:54:34 AM UTC 24 Sep 24 08:54:36 AM UTC 24 167434574 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.1915481006 Sep 24 08:54:34 AM UTC 24 Sep 24 08:54:36 AM UTC 24 167701389 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.4240769339 Sep 24 08:54:35 AM UTC 24 Sep 24 08:54:38 AM UTC 24 185075404 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.1905784474 Sep 24 08:54:07 AM UTC 24 Sep 24 08:54:38 AM UTC 24 3987841853 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.901639361 Sep 24 08:54:10 AM UTC 24 Sep 24 08:54:38 AM UTC 24 1947289524 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.1637596804 Sep 24 08:54:36 AM UTC 24 Sep 24 08:54:39 AM UTC 24 238212990 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.2539769907 Sep 24 08:54:08 AM UTC 24 Sep 24 08:54:39 AM UTC 24 3646926447 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.3249489062 Sep 24 08:54:20 AM UTC 24 Sep 24 08:54:40 AM UTC 24 4908684471 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.3489604071 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:41 AM UTC 24 4321346363 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_enable.3029559647 Sep 24 08:54:40 AM UTC 24 Sep 24 08:54:42 AM UTC 24 39257154 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.1815756721 Sep 24 08:54:40 AM UTC 24 Sep 24 08:54:42 AM UTC 24 147220130 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.3971605301 Sep 24 08:54:36 AM UTC 24 Sep 24 08:54:43 AM UTC 24 993387711 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.3332180990 Sep 24 08:54:40 AM UTC 24 Sep 24 08:54:44 AM UTC 24 593242154 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1634280074 Sep 24 08:54:41 AM UTC 24 Sep 24 08:54:45 AM UTC 24 511846005 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.2652438393 Sep 24 08:54:42 AM UTC 24 Sep 24 08:54:45 AM UTC 24 171684312 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.4051089353 Sep 24 08:54:41 AM UTC 24 Sep 24 08:54:47 AM UTC 24 807974392 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.2496755599 Sep 24 08:54:43 AM UTC 24 Sep 24 08:54:47 AM UTC 24 231415415 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2724550721 Sep 24 08:54:04 AM UTC 24 Sep 24 08:54:48 AM UTC 24 5158221797 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.1785176485 Sep 24 08:54:23 AM UTC 24 Sep 24 08:54:49 AM UTC 24 1944962082 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.2355285259 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:50 AM UTC 24 1444504969 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.2646661940 Sep 24 08:54:17 AM UTC 24 Sep 24 08:54:50 AM UTC 24 9921340314 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.1246063795 Sep 24 08:54:09 AM UTC 24 Sep 24 08:54:50 AM UTC 24 3533149748 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.1837590280 Sep 24 08:54:48 AM UTC 24 Sep 24 08:54:50 AM UTC 24 187619158 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.4254524220 Sep 24 08:54:49 AM UTC 24 Sep 24 08:54:51 AM UTC 24 137368219 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.826314948 Sep 24 08:54:50 AM UTC 24 Sep 24 08:54:53 AM UTC 24 209339290 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.499222762 Sep 24 08:54:51 AM UTC 24 Sep 24 08:54:54 AM UTC 24 204591535 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.2656686459 Sep 24 08:54:38 AM UTC 24 Sep 24 08:54:56 AM UTC 24 1384574690 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.1956941103 Sep 24 08:54:03 AM UTC 24 Sep 24 08:54:57 AM UTC 24 29596261335 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.791981292 Sep 24 08:54:55 AM UTC 24 Sep 24 08:54:58 AM UTC 24 242615218 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.998215545 Sep 24 08:54:57 AM UTC 24 Sep 24 08:55:00 AM UTC 24 219571200 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.108726320 Sep 24 08:54:20 AM UTC 24 Sep 24 08:55:06 AM UTC 24 20168680732 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.2946821571 Sep 24 08:54:37 AM UTC 24 Sep 24 08:55:07 AM UTC 24 996109610 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.1645991117 Sep 24 08:54:52 AM UTC 24 Sep 24 08:55:08 AM UTC 24 10487718615 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.2060214922 Sep 24 08:55:07 AM UTC 24 Sep 24 08:55:10 AM UTC 24 166714463 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.22214000 Sep 24 08:55:07 AM UTC 24 Sep 24 08:55:10 AM UTC 24 152443593 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.2628480169 Sep 24 08:54:30 AM UTC 24 Sep 24 08:55:10 AM UTC 24 11873288658 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.455236730 Sep 24 08:55:09 AM UTC 24 Sep 24 08:55:11 AM UTC 24 170691803 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.4255993549 Sep 24 08:54:18 AM UTC 24 Sep 24 08:55:13 AM UTC 24 5635090174 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.1179439229 Sep 24 08:55:11 AM UTC 24 Sep 24 08:55:13 AM UTC 24 156187365 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.958161637 Sep 24 08:55:11 AM UTC 24 Sep 24 08:55:13 AM UTC 24 196681639 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.370173386 Sep 24 08:55:11 AM UTC 24 Sep 24 08:55:14 AM UTC 24 227751026 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.2150066314 Sep 24 08:55:12 AM UTC 24 Sep 24 08:55:15 AM UTC 24 214652920 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.2786089821 Sep 24 08:55:14 AM UTC 24 Sep 24 08:55:17 AM UTC 24 160659006 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.1998472251 Sep 24 08:55:14 AM UTC 24 Sep 24 08:55:17 AM UTC 24 238556192 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.2757406383 Sep 24 08:55:14 AM UTC 24 Sep 24 08:55:17 AM UTC 24 222616997 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2547389797 Sep 24 08:54:03 AM UTC 24 Sep 24 08:55:17 AM UTC 24 27342319681 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.2717680279 Sep 24 08:55:15 AM UTC 24 Sep 24 08:55:18 AM UTC 24 75967085 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.35597321 Sep 24 08:55:18 AM UTC 24 Sep 24 08:55:20 AM UTC 24 177486812 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.2290494820 Sep 24 08:55:18 AM UTC 24 Sep 24 08:55:20 AM UTC 24 181906409 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.2214306520 Sep 24 08:54:58 AM UTC 24 Sep 24 08:55:21 AM UTC 24 2067139012 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.2285572362 Sep 24 08:54:31 AM UTC 24 Sep 24 08:55:21 AM UTC 24 21193250591 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.3219045184 Sep 24 08:54:48 AM UTC 24 Sep 24 08:55:21 AM UTC 24 2818361058 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.3321195432 Sep 24 08:55:19 AM UTC 24 Sep 24 08:55:22 AM UTC 24 177500488 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.3333662577 Sep 24 08:55:19 AM UTC 24 Sep 24 08:55:22 AM UTC 24 206809544 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.1129264404 Sep 24 08:55:22 AM UTC 24 Sep 24 08:55:25 AM UTC 24 156748946 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.56244673 Sep 24 08:55:22 AM UTC 24 Sep 24 08:55:25 AM UTC 24 318727092 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.3780003458 Sep 24 08:55:23 AM UTC 24 Sep 24 08:55:26 AM UTC 24 179514450 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.1518718337 Sep 24 08:54:54 AM UTC 24 Sep 24 08:55:27 AM UTC 24 2473859165 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.358813994 Sep 24 08:55:23 AM UTC 24 Sep 24 08:55:27 AM UTC 24 422321199 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.51898422 Sep 24 08:54:53 AM UTC 24 Sep 24 08:55:28 AM UTC 24 3050103220 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.2185719688 Sep 24 08:55:25 AM UTC 24 Sep 24 08:55:28 AM UTC 24 225898349 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.1877570124 Sep 24 08:55:26 AM UTC 24 Sep 24 08:55:29 AM UTC 24 163571974 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.1222993214 Sep 24 08:55:26 AM UTC 24 Sep 24 08:55:29 AM UTC 24 159838075 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.2971059191 Sep 24 08:55:29 AM UTC 24 Sep 24 08:55:32 AM UTC 24 210218358 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.328515428 Sep 24 08:54:20 AM UTC 24 Sep 24 08:55:32 AM UTC 24 2105602442 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.1869608408 Sep 24 08:55:30 AM UTC 24 Sep 24 08:55:33 AM UTC 24 178479430 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.4245573904 Sep 24 08:55:30 AM UTC 24 Sep 24 08:55:33 AM UTC 24 154600748 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.2450192079 Sep 24 08:54:59 AM UTC 24 Sep 24 08:55:34 AM UTC 24 3329140372 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.2464409524 Sep 24 08:55:30 AM UTC 24 Sep 24 08:55:35 AM UTC 24 1101267081 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.3854897288 Sep 24 08:55:33 AM UTC 24 Sep 24 08:55:37 AM UTC 24 462670551 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.3325738206 Sep 24 08:55:36 AM UTC 24 Sep 24 08:55:38 AM UTC 24 33582476 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.744507201 Sep 24 08:55:35 AM UTC 24 Sep 24 08:55:40 AM UTC 24 1826372296 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.443846897 Sep 24 08:55:39 AM UTC 24 Sep 24 08:55:42 AM UTC 24 160025435 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.283518853 Sep 24 08:55:41 AM UTC 24 Sep 24 08:55:43 AM UTC 24 164111350 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.954512100 Sep 24 08:55:41 AM UTC 24 Sep 24 08:55:44 AM UTC 24 200208781 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.4022008975 Sep 24 08:54:32 AM UTC 24 Sep 24 08:55:44 AM UTC 24 26280777313 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.3394211743 Sep 24 08:55:42 AM UTC 24 Sep 24 08:55:45 AM UTC 24 169184454 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.2240956973 Sep 24 08:55:45 AM UTC 24 Sep 24 08:55:47 AM UTC 24 184068168 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.434384810 Sep 24 08:55:45 AM UTC 24 Sep 24 08:55:49 AM UTC 24 758464599 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.652720773 Sep 24 08:55:36 AM UTC 24 Sep 24 08:55:50 AM UTC 24 5553721346 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.2587836056 Sep 24 08:55:51 AM UTC 24 Sep 24 08:55:54 AM UTC 24 156386606 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.3106623777 Sep 24 08:55:50 AM UTC 24 Sep 24 08:55:54 AM UTC 24 561322941 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_enable.3996592430 Sep 24 08:55:54 AM UTC 24 Sep 24 08:55:56 AM UTC 24 47704680 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.609583349 Sep 24 08:55:55 AM UTC 24 Sep 24 08:56:00 AM UTC 24 641519597 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.246928088 Sep 24 08:55:22 AM UTC 24 Sep 24 08:56:00 AM UTC 24 6479236675 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.2492911646 Sep 24 08:55:57 AM UTC 24 Sep 24 08:56:00 AM UTC 24 206979983 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.3554626813 Sep 24 08:55:54 AM UTC 24 Sep 24 08:56:00 AM UTC 24 842140008 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.3920352393 Sep 24 08:55:15 AM UTC 24 Sep 24 08:56:02 AM UTC 24 9131359750 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.3654590482 Sep 24 08:54:05 AM UTC 24 Sep 24 08:56:03 AM UTC 24 3040822211 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.1372940347 Sep 24 08:55:48 AM UTC 24 Sep 24 08:56:03 AM UTC 24 1082762288 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.3319780627 Sep 24 08:56:01 AM UTC 24 Sep 24 08:56:05 AM UTC 24 274185749 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.4219508656 Sep 24 08:56:06 AM UTC 24 Sep 24 08:56:09 AM UTC 24 296376176 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3094903615 Sep 24 08:55:00 AM UTC 24 Sep 24 08:56:10 AM UTC 24 2054857079 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.2648572291 Sep 24 08:56:10 AM UTC 24 Sep 24 08:56:13 AM UTC 24 181654091 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.791256700 Sep 24 08:56:11 AM UTC 24 Sep 24 08:56:14 AM UTC 24 229248987 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.3636729477 Sep 24 08:55:46 AM UTC 24 Sep 24 08:56:14 AM UTC 24 4270186852 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2178377610 Sep 24 08:54:37 AM UTC 24 Sep 24 08:56:16 AM UTC 24 47520967277 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.3822817828 Sep 24 08:56:14 AM UTC 24 Sep 24 08:56:17 AM UTC 24 256036602 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.3066713812 Sep 24 08:54:25 AM UTC 24 Sep 24 08:56:18 AM UTC 24 2647477611 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.835109122 Sep 24 08:54:26 AM UTC 24 Sep 24 08:56:22 AM UTC 24 3503220108 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.2249058913 Sep 24 08:56:23 AM UTC 24 Sep 24 08:56:26 AM UTC 24 280166464 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.177861114 Sep 24 08:55:38 AM UTC 24 Sep 24 08:56:27 AM UTC 24 30909358738 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.2163191806 Sep 24 08:56:27 AM UTC 24 Sep 24 08:56:30 AM UTC 24 208000040 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.2318874074 Sep 24 08:55:33 AM UTC 24 Sep 24 08:56:34 AM UTC 24 7887461696 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.1523933810 Sep 24 08:54:51 AM UTC 24 Sep 24 08:56:36 AM UTC 24 26138122862 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.192675790 Sep 24 08:55:29 AM UTC 24 Sep 24 08:56:36 AM UTC 24 2035629268 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.1319463707 Sep 24 08:55:22 AM UTC 24 Sep 24 08:56:37 AM UTC 24 20175397045 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.2452664839 Sep 24 08:56:37 AM UTC 24 Sep 24 08:56:39 AM UTC 24 156273359 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.699233404 Sep 24 08:56:37 AM UTC 24 Sep 24 08:56:39 AM UTC 24 156732808 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.4101996974 Sep 24 08:56:38 AM UTC 24 Sep 24 08:56:40 AM UTC 24 169387791 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.125398602 Sep 24 08:55:36 AM UTC 24 Sep 24 08:56:41 AM UTC 24 20533082117 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.3420044558 Sep 24 08:56:40 AM UTC 24 Sep 24 08:56:43 AM UTC 24 207511589 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.2109374224 Sep 24 08:56:40 AM UTC 24 Sep 24 08:56:44 AM UTC 24 228014540 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.220867546 Sep 24 08:56:41 AM UTC 24 Sep 24 08:56:44 AM UTC 24 153134213 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.3101272592 Sep 24 08:56:41 AM UTC 24 Sep 24 08:56:44 AM UTC 24 189337540 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.3986106813 Sep 24 08:56:44 AM UTC 24 Sep 24 08:56:48 AM UTC 24 168458442 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.2966889833 Sep 24 08:56:44 AM UTC 24 Sep 24 08:56:48 AM UTC 24 247981429 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.670703177 Sep 24 08:56:44 AM UTC 24 Sep 24 08:56:48 AM UTC 24 241265762 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.272335078 Sep 24 08:56:46 AM UTC 24 Sep 24 08:56:48 AM UTC 24 50592861 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.2145929765 Sep 24 08:56:13 AM UTC 24 Sep 24 08:56:51 AM UTC 24 5049000353 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.1444067485 Sep 24 08:54:51 AM UTC 24 Sep 24 08:56:51 AM UTC 24 11230609767 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.799142591 Sep 24 08:56:49 AM UTC 24 Sep 24 08:56:51 AM UTC 24 162751084 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.3675535013 Sep 24 08:56:49 AM UTC 24 Sep 24 08:56:52 AM UTC 24 229671580 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.3932619234 Sep 24 08:56:49 AM UTC 24 Sep 24 08:56:52 AM UTC 24 208237934 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.210023373 Sep 24 08:56:17 AM UTC 24 Sep 24 08:56:52 AM UTC 24 9794642117 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.2846709902 Sep 24 08:55:45 AM UTC 24 Sep 24 08:56:55 AM UTC 24 30056686320 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.790405247 Sep 24 08:56:52 AM UTC 24 Sep 24 08:56:55 AM UTC 24 164710507 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.1927915252 Sep 24 08:56:54 AM UTC 24 Sep 24 08:56:56 AM UTC 24 139384923 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.2122385105 Sep 24 08:56:31 AM UTC 24 Sep 24 08:56:59 AM UTC 24 2353787175 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.1998037438 Sep 24 08:56:56 AM UTC 24 Sep 24 08:56:59 AM UTC 24 194546098 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.567535995 Sep 24 08:56:56 AM UTC 24 Sep 24 08:56:59 AM UTC 24 278005600 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.3138454259 Sep 24 08:55:22 AM UTC 24 Sep 24 08:56:59 AM UTC 24 6451173978 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.1371115691 Sep 24 08:55:30 AM UTC 24 Sep 24 08:57:53 AM UTC 24 4103290825 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.3979069449 Sep 24 08:56:58 AM UTC 24 Sep 24 08:57:02 AM UTC 24 434568951 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.3032180940 Sep 24 08:57:00 AM UTC 24 Sep 24 08:57:03 AM UTC 24 149054252 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.518171304 Sep 24 08:57:00 AM UTC 24 Sep 24 08:57:03 AM UTC 24 160381810 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.1609857048 Sep 24 08:57:00 AM UTC 24 Sep 24 08:57:03 AM UTC 24 193014995 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.3357594156 Sep 24 08:56:18 AM UTC 24 Sep 24 08:57:03 AM UTC 24 4426186372 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.3231614817 Sep 24 08:57:01 AM UTC 24 Sep 24 08:57:04 AM UTC 24 200883256 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.3149096344 Sep 24 08:57:03 AM UTC 24 Sep 24 08:57:06 AM UTC 24 157373656 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.2169561927 Sep 24 08:57:03 AM UTC 24 Sep 24 08:57:06 AM UTC 24 171789735 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.359234936 Sep 24 08:55:19 AM UTC 24 Sep 24 08:57:10 AM UTC 24 6928067195 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.3138176464 Sep 24 08:58:18 AM UTC 24 Sep 24 08:58:21 AM UTC 24 198735784 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.1119900823 Sep 24 08:57:07 AM UTC 24 Sep 24 08:57:11 AM UTC 24 580340271 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.3194844391 Sep 24 08:57:05 AM UTC 24 Sep 24 08:57:13 AM UTC 24 1421996241 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.1387323697 Sep 24 08:57:12 AM UTC 24 Sep 24 08:57:15 AM UTC 24 56141419 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.3285078138 Sep 24 08:56:49 AM UTC 24 Sep 24 08:57:16 AM UTC 24 8429594273 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.3042051795 Sep 24 08:57:11 AM UTC 24 Sep 24 08:57:16 AM UTC 24 943387537 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.3388044766 Sep 24 08:56:35 AM UTC 24 Sep 24 08:57:17 AM UTC 24 2717157599 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.1323064472 Sep 24 08:57:17 AM UTC 24 Sep 24 08:57:20 AM UTC 24 182126290 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.2698059803 Sep 24 08:57:17 AM UTC 24 Sep 24 08:57:20 AM UTC 24 220044430 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.3649522893 Sep 24 08:57:18 AM UTC 24 Sep 24 08:57:21 AM UTC 24 140638582 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.1571945942 Sep 24 08:57:20 AM UTC 24 Sep 24 08:57:23 AM UTC 24 146538653 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.3128405098 Sep 24 08:56:14 AM UTC 24 Sep 24 08:57:24 AM UTC 24 29817104124 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.3426363870 Sep 24 08:57:20 AM UTC 24 Sep 24 08:57:24 AM UTC 24 437837870 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.3729847129 Sep 24 08:57:21 AM UTC 24 Sep 24 08:57:24 AM UTC 24 376383020 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.4252291461 Sep 24 08:57:25 AM UTC 24 Sep 24 08:57:30 AM UTC 24 783317361 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.2926880740 Sep 24 08:54:05 AM UTC 24 Sep 24 08:57:31 AM UTC 24 87052029970 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.3678889460 Sep 24 08:57:31 AM UTC 24 Sep 24 08:57:34 AM UTC 24 164022020 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.4104208052 Sep 24 08:56:28 AM UTC 24 Sep 24 08:57:34 AM UTC 24 2080265591 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.1869659838 Sep 24 08:56:52 AM UTC 24 Sep 24 08:57:34 AM UTC 24 5678520864 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_enable.2700049172 Sep 24 08:57:33 AM UTC 24 Sep 24 08:57:35 AM UTC 24 33661241 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.1682180285 Sep 24 08:56:20 AM UTC 24 Sep 24 08:57:36 AM UTC 24 2443170643 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.2871041055 Sep 24 08:57:35 AM UTC 24 Sep 24 08:57:38 AM UTC 24 273927862 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.835493779 Sep 24 08:57:35 AM UTC 24 Sep 24 08:57:39 AM UTC 24 632394238 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.1729153917 Sep 24 08:57:35 AM UTC 24 Sep 24 08:57:41 AM UTC 24 762913198 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.2989876053 Sep 24 08:57:36 AM UTC 24 Sep 24 08:57:41 AM UTC 24 318583027 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.4000217215 Sep 24 08:57:12 AM UTC 24 Sep 24 08:57:41 AM UTC 24 11544519248 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.1345832068 Sep 24 08:57:43 AM UTC 24 Sep 24 08:57:46 AM UTC 24 177664492 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.2773335430 Sep 24 08:56:53 AM UTC 24 Sep 24 08:57:48 AM UTC 24 20165298563 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.3304396919 Sep 24 08:57:47 AM UTC 24 Sep 24 08:57:50 AM UTC 24 138384357 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.840604918 Sep 24 08:57:48 AM UTC 24 Sep 24 08:57:51 AM UTC 24 222690552 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.1912006354 Sep 24 08:57:25 AM UTC 24 Sep 24 08:57:52 AM UTC 24 2036990561 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.2417577135 Sep 24 08:57:03 AM UTC 24 Sep 24 08:57:52 AM UTC 24 3152899552 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.1712812224 Sep 24 08:57:52 AM UTC 24 Sep 24 08:57:54 AM UTC 24 209623633 ps
T658 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.941342217 Sep 24 08:54:05 AM UTC 24 Sep 24 08:58:09 AM UTC 24 107120600027 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.1914262492 Sep 24 08:57:25 AM UTC 24 Sep 24 08:58:10 AM UTC 24 3866754461 ps
T660 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.68523752 Sep 24 08:56:04 AM UTC 24 Sep 24 08:58:11 AM UTC 24 3519447236 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.3793383355 Sep 24 08:54:05 AM UTC 24 Sep 24 08:58:12 AM UTC 24 114185175947 ps
T661 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3251965347 Sep 24 08:58:10 AM UTC 24 Sep 24 08:58:13 AM UTC 24 248210559 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.868289428 Sep 24 08:57:24 AM UTC 24 Sep 24 08:58:13 AM UTC 24 27585030419 ps
T662 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.3119663235 Sep 24 08:58:11 AM UTC 24 Sep 24 08:58:14 AM UTC 24 208621799 ps
T663 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.2114095677 Sep 24 08:57:53 AM UTC 24 Sep 24 08:58:16 AM UTC 24 6186444323 ps
T664 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.357493717 Sep 24 08:58:15 AM UTC 24 Sep 24 08:58:18 AM UTC 24 167201195 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.1056396856 Sep 24 08:58:15 AM UTC 24 Sep 24 08:58:18 AM UTC 24 154653032 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.756472703 Sep 24 08:57:13 AM UTC 24 Sep 24 08:58:19 AM UTC 24 20946831091 ps
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