Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	807	1			T33	8		T112	1		T108	7
range_16_to_126	158032	1			T1	1		T2	1		T28	8
fifteen	3917	1			T108	7		T121	3		T122	6
range_2_to_14	18455	1			T3	1		T43	3		T32	2
seven	2536	1			T108	1		T422	1		T121	6
one	386	1			T120	1		T108	2		T423	2
zero	866	1			T42	1		T424	1		T295	5

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13036

1

T43

1

T34

2

T37

3

three

12704

1

T43

1

T34

2

T37

1

---

Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	45	1			T108	1		T168	7		T122	1
range_127	three	87	1			T168	7		T177	1		T425	3
range_16_to_126	seven	11239	1			T43	1		T34	2		T37	3
range_16_to_126	three	10981	1			T43	1		T34	2		T37	1
fifteen	seven	251	1			T108	1		T426	35		T427	1
fifteen	three	341	1			T122	1		T177	1		T426	41
range_2_to_14	seven	1381	1			T70	7		T428	2		T185	7
range_2_to_14	three	1232	1			T4	17		T428	2		T108	4
seven	seven	220	1			T122	1		T180	1		T429	21
seven	three	211	1			T121	1		T177	1		T430	1
one	seven	97	1			T121	1		T180	1		T431	1
one	three	21	1			T121	1		T122	1		T300	2
zero	seven	23	1			T86	1		T121	1		T122	1
zero	three	42	1			T432	1		T302	4		T433	27