Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114003

1

T1

1

T2

1

T3

1

auto[1]

45244

1

T30

1

T32

1

T34

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29743	1			T29	1		T38	2		T88	1
max_len_m1	874	1			T36	1		T37	1		T18	2
max_len_m2	844	1			T29	1		T18	4		T114	2
max_len_m3	805	1			T74	1		T18	3		T57	1
five	1121	1			T37	1		T18	1		T65	1
four	1151	1			T22	1		T420	1		T123	3
three	677	1			T36	4		T18	3		T107	5
one	784	1			T74	1		T18	3		T123	1
zero	11143	1			T42	1		T37	8		T419	1

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24098	1			T29	1		T38	1		T88	1
max_len	auto[1]	5645	1			T38	1		T6	47		T123	1
max_len_m1	auto[0]	594	1			T36	1		T37	1		T18	2
max_len_m1	auto[1]	280	1			T4	1		T123	1		T184	1
max_len_m2	auto[0]	572	1			T29	1		T18	4		T114	1
max_len_m2	auto[1]	272	1			T114	1		T184	4		T170	2
max_len_m3	auto[0]	549	1			T74	1		T18	3		T57	1
max_len_m3	auto[1]	256	1			T114	1		T70	1		T184	2
five	auto[0]	586	1			T37	1		T18	1		T5	1
five	auto[1]	535	1			T65	1		T5	1		T114	2
four	auto[0]	583	1			T22	1		T420	1		T123	2
four	auto[1]	568	1			T123	1		T175	1		T107	4
three	auto[0]	341	1			T36	4		T18	3		T107	2
three	auto[1]	336	1			T107	3		T434	1		T252	3
one	auto[0]	383	1			T74	1		T18	3		T123	1
one	auto[1]	401	1			T107	3		T252	5		T14	1
zero	auto[0]	519	1			T42	1		T419	1		T162	1
zero	auto[1]	10624	1			T37	8		T162	1		T50	1