Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138010

1

T1

2

T2

2

T3

2

auto[1]

76785

1

T32

2

T34

24

T35

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	17925	1			T28	15		T34	4		T37	2
endpoints[0x1]	20496	1			T2	2		T34	4		T37	8
endpoints[0x2]	22121	1			T33	16		T34	4		T35	4
endpoints[0x3]	15390	1			T34	4		T37	2		T88	2
endpoints[0x4]	14167	1			T32	4		T34	4		T37	5
endpoints[0x5]	20111	1			T1	2		T30	2		T34	4
endpoints[0x6]	20669	1			T34	4		T37	13		T74	21
endpoints[0x7]	17803	1			T34	4		T37	6		T162	4
endpoints[0x8]	16175	1			T29	21		T34	4		T37	8
endpoints[0x9]	18713	1			T34	4		T37	8		T38	4
endpoints[0xa]	15439	1			T34	4		T37	3		T65	13
endpoints[0xb]	15786	1			T3	2		T34	4		T37	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1416	1			T29	2		T36	2		T37	8
ack	104002	1			T1	1		T2	1		T3	1
data1	50618	1			T1	1		T28	1		T29	5
data0	58690	1			T2	1		T3	1		T28	7

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	162	1			T108	9		T121	11		T122	12
nak	auto[0]	endpoints[0x1]	99	1			T55	1		T435	1		T108	9
nak	auto[0]	endpoints[0x2]	91	1			T36	2		T122	10		T177	10
nak	auto[0]	endpoints[0x3]	66	1			T436	1		T437	15		T432	18
nak	auto[0]	endpoints[0x4]	97	1			T122	4		T177	9		T438	1
nak	auto[0]	endpoints[0x5]	101	1			T143	1		T300	3		T426	11
nak	auto[0]	endpoints[0x6]	172	1			T74	2		T146	1		T121	17
nak	auto[0]	endpoints[0x7]	79	1			T108	7		T439	1		T440	1
nak	auto[0]	endpoints[0x8]	77	1			T29	2		T75	1		T421	1
nak	auto[0]	endpoints[0x9]	83	1			T316	1		T300	7		T180	9
nak	auto[0]	endpoints[0xa]	108	1			T177	3		T156	1		T157	1
nak	auto[0]	endpoints[0xb]	113	1			T177	8		T431	11		T437	21
nak	auto[1]	endpoints[0x0]	14	1			T441	1		T442	1		T443	1
nak	auto[1]	endpoints[0x1]	11	1			T37	1		T119	1		T441	1
nak	auto[1]	endpoints[0x2]	10	1			T115	1		T444	1		T445	1
nak	auto[1]	endpoints[0x3]	18	1			T37	1		T445	1		T446	2
nak	auto[1]	endpoints[0x4]	18	1			T37	1		T115	2		T447	1
nak	auto[1]	endpoints[0x5]	10	1			T37	1		T115	1		T445	1
nak	auto[1]	endpoints[0x6]	22	1			T119	1		T448	1		T445	1
nak	auto[1]	endpoints[0x7]	11	1			T37	2		T115	1		T448	1
nak	auto[1]	endpoints[0x8]	10	1			T37	1		T449	2		T450	1
nak	auto[1]	endpoints[0x9]	16	1			T37	1		T115	1		T451	1
nak	auto[1]	endpoints[0xa]	16	1			T449	2		T451	1		T448	1
nak	auto[1]	endpoints[0xb]	12	1			T119	1		T443	1		T452	1
ack	auto[0]	endpoints[0x0]	5524	1			T28	7		T34	1		T37	1
ack	auto[0]	endpoints[0x1]	6558	1			T2	1		T34	1		T37	2
ack	auto[0]	endpoints[0x2]	7893	1			T33	8		T34	1		T35	1
ack	auto[0]	endpoints[0x3]	4338	1			T34	1		T88	1		T419	1
ack	auto[0]	endpoints[0x4]	3619	1			T32	1		T34	1		T91	1
ack	auto[0]	endpoints[0x5]	6482	1			T1	1		T30	1		T34	1
ack	auto[0]	endpoints[0x6]	7016	1			T34	1		T37	4		T74	8
ack	auto[0]	endpoints[0x7]	5384	1			T34	1		T37	1		T162	1
ack	auto[0]	endpoints[0x8]	4613	1			T29	8		T34	1		T37	2
ack	auto[0]	endpoints[0x9]	5828	1			T34	1		T37	2		T38	1
ack	auto[0]	endpoints[0xa]	4437	1			T34	1		T37	1		T65	4
ack	auto[0]	endpoints[0xb]	4497	1			T3	1		T34	1		T37	1
ack	auto[1]	endpoints[0x0]	3106	1			T34	1		T24	1		T4	8
ack	auto[1]	endpoints[0x1]	3382	1			T34	1		T37	1		T51	1
ack	auto[1]	endpoints[0x2]	2934	1			T34	1		T5	3		T123	8
ack	auto[1]	endpoints[0x3]	3131	1			T34	1		T4	8		T5	3
ack	auto[1]	endpoints[0x4]	3186	1			T32	1		T34	1		T37	1
ack	auto[1]	endpoints[0x5]	3247	1			T34	1		T50	1		T166	1
ack	auto[1]	endpoints[0x6]	2962	1			T34	1		T37	2		T4	8
ack	auto[1]	endpoints[0x7]	3259	1			T34	1		T162	1		T5	3
ack	auto[1]	endpoints[0x8]	3215	1			T34	1		T37	1		T23	1
ack	auto[1]	endpoints[0x9]	3251	1			T34	1		T37	1		T38	1
ack	auto[1]	endpoints[0xa]	3016	1			T34	1		T65	2		T5	3
ack	auto[1]	endpoints[0xb]	3124	1			T34	1		T123	8		T70	3
data1	auto[0]	endpoints[0x0]	2472	1			T28	1		T37	1		T4	4
data1	auto[0]	endpoints[0x1]	2977	1			T37	1		T51	1		T55	4
data1	auto[0]	endpoints[0x2]	3690	1			T36	5		T37	2		T123	2
data1	auto[0]	endpoints[0x3]	1909	1			T96	6		T5	1		T123	3
data1	auto[0]	endpoints[0x4]	1524	1			T21	1		T5	1		T70	1
data1	auto[0]	endpoints[0x5]	2963	1			T1	1		T37	1		T50	1
data1	auto[0]	endpoints[0x6]	3291	1			T37	2		T74	5		T4	3
data1	auto[0]	endpoints[0x7]	2369	1			T5	1		T107	7		T170	4
data1	auto[0]	endpoints[0x8]	1981	1			T29	5		T37	1		T75	1
data1	auto[0]	endpoints[0x9]	2621	1			T37	1		T48	1		T57	3
data1	auto[0]	endpoints[0xa]	1951	1			T37	1		T65	2		T5	1
data1	auto[0]	endpoints[0xb]	1947	1			T37	1		T116	1		T123	3
data1	auto[1]	endpoints[0x0]	1719	1			T4	4		T5	2		T70	1
data1	auto[1]	endpoints[0x1]	1870	1			T51	1		T114	18		T70	3
data1	auto[1]	endpoints[0x2]	1624	1			T5	2		T123	6		T70	1
data1	auto[1]	endpoints[0x3]	1730	1			T4	4		T5	2		T123	5
data1	auto[1]	endpoints[0x4]	1742	1			T21	1		T5	2		T70	1
data1	auto[1]	endpoints[0x5]	1779	1			T50	1		T166	1		T4	4
data1	auto[1]	endpoints[0x6]	1643	1			T37	2		T4	5		T5	1
data1	auto[1]	endpoints[0x7]	1820	1			T37	1		T5	1		T70	3
data1	auto[1]	endpoints[0x8]	1787	1			T37	2		T4	5		T123	4
data1	auto[1]	endpoints[0x9]	1809	1			T37	1		T48	1		T65	1
data1	auto[1]	endpoints[0xa]	1668	1			T65	2		T5	1		T123	4
data1	auto[1]	endpoints[0xb]	1732	1			T123	4		T70	1		T175	2
data0	auto[0]	endpoints[0x0]	3480	1			T28	7		T34	1		T24	1
data0	auto[0]	endpoints[0x1]	4007	1			T2	1		T34	1		T37	1
data0	auto[0]	endpoints[0x2]	4490	1			T33	8		T34	1		T35	1
data0	auto[0]	endpoints[0x3]	2695	1			T34	1		T88	1		T419	1
data0	auto[0]	endpoints[0x4]	2465	1			T32	1		T34	1		T91	1
data0	auto[0]	endpoints[0x5]	3991	1			T30	1		T34	1		T50	1
data0	auto[0]	endpoints[0x6]	4148	1			T34	1		T37	2		T74	6
data0	auto[0]	endpoints[0x7]	3369	1			T34	1		T37	1		T162	1
data0	auto[0]	endpoints[0x8]	2989	1			T29	6		T34	1		T37	1
data0	auto[0]	endpoints[0x9]	3544	1			T34	1		T37	1		T38	1
data0	auto[0]	endpoints[0xa]	2819	1			T34	1		T65	2		T5	2
data0	auto[0]	endpoints[0xb]	2862	1			T3	1		T34	1		T90	1
data0	auto[1]	endpoints[0x0]	1445	1			T34	1		T24	1		T4	4
data0	auto[1]	endpoints[0x1]	1584	1			T34	1		T37	2		T114	19
data0	auto[1]	endpoints[0x2]	1380	1			T34	1		T35	1		T5	1
data0	auto[1]	endpoints[0x3]	1500	1			T34	1		T37	1		T4	4
data0	auto[1]	endpoints[0x4]	1511	1			T32	1		T34	1		T37	3
data0	auto[1]	endpoints[0x5]	1531	1			T34	1		T37	1		T4	4
data0	auto[1]	endpoints[0x6]	1412	1			T34	1		T37	1		T4	3
data0	auto[1]	endpoints[0x7]	1510	1			T34	1		T37	1		T162	1
data0	auto[1]	endpoints[0x8]	1498	1			T34	1		T23	1		T4	3
data0	auto[1]	endpoints[0x9]	1557	1			T34	1		T37	1		T38	1
data0	auto[1]	endpoints[0xa]	1417	1			T34	1		T37	1		T65	1
data0	auto[1]	endpoints[0xb]	1486	1			T34	1		T123	4		T70	2