Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8834 1 T43 4 T87 3 T123 1
auto[1] 53730 1 T43 1 T30 1 T31 1


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54715 1 T43 4 T31 1 T32 1
auto[1] 7849 1 T43 1 T30 1 T6 49


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56266 1 T43 3 T30 1 T32 1
auto[1] 6298 1 T43 2 T31 1 T87 3


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4629 1 T43 1 T87 1 T123 5
pkt_types[PidTypeInToken] 57935 1 T43 4 T30 1 T31 1


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1462 1 T43 1 T108 28 T453 2
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 739 1 T424 1 T108 19 T121 30
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 101 1 T123 1 T198 2 T454 1
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 12 1 T455 1 T456 1 T457 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1428 1 T87 1 T123 3 T108 14
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 791 1 T121 47 T122 27 T458 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 84 1 T123 1 T198 2 T423 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 12 1 T423 1 T459 1 T460 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4214 1 T43 2 T424 4 T108 131
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2204 1 T43 1 T87 3 T424 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 56 1 T120 1 T461 1 T462 2
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 46 1 T463 1 T464 1 T465 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41433 1 T32 1 T34 12 T35 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2444 1 T31 1 T112 1 T113 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7488 1 T30 1 T6 49 T123 18
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 50 1 T43 1 T120 1 T423 1

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