Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81770	1			T1	2		T2	6		T3	4
all_pins[1]	81770	1			T1	2		T2	6		T3	4
all_pins[2]	81770	1			T1	2		T2	6		T3	4
all_pins[3]	81770	1			T1	2		T2	6		T3	4
all_pins[4]	81770	1			T1	2		T2	6		T3	4
all_pins[5]	81770	1			T1	2		T2	6		T3	4
all_pins[6]	81770	1			T1	2		T2	6		T3	4
all_pins[7]	81770	1			T1	2		T2	6		T3	4
all_pins[8]	81770	1			T1	2		T2	6		T3	4
all_pins[9]	81770	1			T1	2		T2	6		T3	4
all_pins[10]	81770	1			T1	2		T2	6		T3	4
all_pins[11]	81770	1			T1	2		T2	6		T3	4
all_pins[12]	81770	1			T1	2		T2	6		T3	4
all_pins[13]	81770	1			T1	2		T2	6		T3	4
all_pins[14]	81770	1			T1	2		T2	6		T3	4
all_pins[15]	81770	1			T1	2		T2	6		T3	4
all_pins[16]	81770	1			T1	2		T2	6		T3	4
all_pins[17]	81770	1			T1	2		T2	6		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2614357	1			T1	64		T2	191		T3	128
values[0x1]	2283	1			T2	1		T39	2		T40	1
transitions[0x0=>0x1]	2034	1			T2	1		T39	2		T40	1
transitions[0x1=>0x0]	2034	1			T2	1		T39	2		T40	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81655	1			T1	2		T2	6		T3	4
all_pins[0]	values[0x1]	115	1			T22	1		T408	1		T409	1
all_pins[0]	transitions[0x0=>0x1]	103	1			T22	1		T408	1		T409	1
all_pins[0]	transitions[0x1=>0x0]	890	1			T32	1		T34	12		T24	1
all_pins[1]	values[0x0]	80868	1			T1	2		T2	6		T3	4
all_pins[1]	values[0x1]	902	1			T32	1		T34	12		T24	1
all_pins[1]	transitions[0x0=>0x1]	888	1			T32	1		T34	12		T24	1
all_pins[1]	transitions[0x1=>0x0]	101	1			T40	1		T68	1		T69	1
all_pins[2]	values[0x0]	81655	1			T1	2		T2	6		T3	4
all_pins[2]	values[0x1]	115	1			T40	1		T68	1		T69	1
all_pins[2]	transitions[0x0=>0x1]	101	1			T40	1		T68	1		T69	1
all_pins[2]	transitions[0x1=>0x0]	36	1			T18	1		T218	1		T314	1
all_pins[3]	values[0x0]	81720	1			T1	2		T2	6		T3	4
all_pins[3]	values[0x1]	50	1			T18	1		T215	1		T218	2
all_pins[3]	transitions[0x0=>0x1]	41	1			T18	1		T218	2		T308	1
all_pins[3]	transitions[0x1=>0x0]	64	1			T49	1		T307	2		T310	3
all_pins[4]	values[0x0]	81697	1			T1	2		T2	6		T3	4
all_pins[4]	values[0x1]	73	1			T49	1		T215	1		T307	2
all_pins[4]	transitions[0x0=>0x1]	60	1			T49	1		T215	1		T307	2
all_pins[4]	transitions[0x1=>0x0]	32	1			T215	2		T217	4		T314	3
all_pins[5]	values[0x0]	81725	1			T1	2		T2	6		T3	4
all_pins[5]	values[0x1]	45	1			T215	2		T217	4		T310	2
all_pins[5]	transitions[0x0=>0x1]	34	1			T215	1		T217	2		T310	2
all_pins[5]	transitions[0x1=>0x0]	113	1			T64	1		T72	1		T73	1
all_pins[6]	values[0x0]	81646	1			T1	2		T2	6		T3	4
all_pins[6]	values[0x1]	124	1			T64	1		T72	1		T73	1
all_pins[6]	transitions[0x0=>0x1]	107	1			T64	1		T72	1		T73	1
all_pins[6]	transitions[0x1=>0x0]	43	1			T52	1		T53	1		T54	1
all_pins[7]	values[0x0]	81710	1			T1	2		T2	6		T3	4
all_pins[7]	values[0x1]	60	1			T52	1		T53	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	41	1			T52	1		T53	1		T54	1
all_pins[7]	transitions[0x1=>0x0]	72	1			T59	1		T60	1		T61	1
all_pins[8]	values[0x0]	81679	1			T1	2		T2	6		T3	4
all_pins[8]	values[0x1]	91	1			T59	1		T60	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	72	1			T59	1		T60	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	62	1			T39	2		T66	2		T67	2
all_pins[9]	values[0x0]	81689	1			T1	2		T2	6		T3	4
all_pins[9]	values[0x1]	81	1			T39	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	66	1			T39	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	44	1			T219	2		T218	2		T217	2
all_pins[10]	values[0x0]	81711	1			T1	2		T2	6		T3	4
all_pins[10]	values[0x1]	59	1			T215	3		T219	2		T218	2
all_pins[10]	transitions[0x0=>0x1]	37	1			T215	3		T219	1		T217	2
all_pins[10]	transitions[0x1=>0x0]	95	1			T76	1		T77	1		T78	1
all_pins[11]	values[0x0]	81653	1			T1	2		T2	6		T3	4
all_pins[11]	values[0x1]	117	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	95	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	55	1			T79	1		T80	1		T82	1
all_pins[12]	values[0x0]	81693	1			T1	2		T2	6		T3	4
all_pins[12]	values[0x1]	77	1			T79	1		T80	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	57	1			T79	1		T80	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	103	1			T42	1		T85	1		T86	1
all_pins[13]	values[0x0]	81647	1			T1	2		T2	6		T3	4
all_pins[13]	values[0x1]	123	1			T42	1		T85	1		T86	1
all_pins[13]	transitions[0x0=>0x1]	107	1			T42	1		T85	1		T86	1
all_pins[13]	transitions[0x1=>0x0]	60	1			T215	1		T219	3		T306	2
all_pins[14]	values[0x0]	81694	1			T1	2		T2	6		T3	4
all_pins[14]	values[0x1]	76	1			T215	1		T219	3		T218	1
all_pins[14]	transitions[0x0=>0x1]	69	1			T219	3		T218	1		T306	2
all_pins[14]	transitions[0x1=>0x0]	40	1			T215	3		T217	1		T308	1
all_pins[15]	values[0x0]	81723	1			T1	2		T2	6		T3	4
all_pins[15]	values[0x1]	47	1			T215	4		T217	1		T308	1
all_pins[15]	transitions[0x0=>0x1]	37	1			T215	4		T308	1		T314	1
all_pins[15]	transitions[0x1=>0x0]	62	1			T29	4		T36	4		T74	4
all_pins[16]	values[0x0]	81698	1			T1	2		T2	6		T3	4
all_pins[16]	values[0x1]	72	1			T29	4		T36	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	63	1			T29	4		T36	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	47	1			T2	1		T62	1		T215	1
all_pins[17]	values[0x0]	81714	1			T1	2		T2	5		T3	4
all_pins[17]	values[0x1]	56	1			T2	1		T62	1		T215	1
all_pins[17]	transitions[0x0=>0x1]	56	1			T2	1		T62	1		T215	1