Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4830	1			T43	1		T120	1		T108	91
invalid_ep[0xd]	4821	1			T43	3		T120	1		T108	80
invalid_ep[0xe]	4849	1			T43	2		T120	1		T108	74
invalid_ep[0xf]	4663	1			T43	1		T120	1		T108	72
endpoints[0x0]	13089	1			T42	1		T28	8		T43	1
endpoints[0x1]	15095	1			T2	1		T34	2		T87	7
endpoints[0x2]	15467	1			T43	3		T33	8		T34	2
endpoints[0x3]	12704	1			T43	1		T34	2		T37	1
endpoints[0x4]	12475	1			T43	1		T32	2		T34	2
endpoints[0x5]	14888	1			T1	1		T30	2		T31	1
endpoints[0x6]	15170	1			T34	2		T87	2		T37	7
endpoints[0x7]	13036	1			T43	1		T34	2		T37	3
endpoints[0x8]	12656	1			T29	11		T34	2		T87	3
endpoints[0x9]	14061	1			T34	2		T87	1		T37	4
endpoints[0xa]	12327	1			T43	2		T34	2		T37	2
endpoints[0xb]	12332	1			T3	1		T43	3		T34	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	25255	1			T2	1		T3	1		T28	7
pkt_types[PidTypeOutToken]	76717	1			T1	1		T42	1		T28	1
pkt_types[PidTypeInToken]	62199	1			T43	7		T30	1		T31	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1055	1			T120	1		T108	27		T121	32
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1059	1			T43	1		T108	17		T121	22
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1090	1			T43	1		T108	15		T423	2
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1044	1			T108	15		T121	32		T122	23
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1788	1			T28	7		T163	1		T55	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1829	1			T2	1		T87	2		T51	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1733	1			T43	1		T33	8		T5	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1717	1			T196	1		T5	1		T123	2
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1734	1			T43	1		T87	3		T91	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1767	1			T50	1		T166	1		T4	3
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1652	1			T4	5		T424	2		T167	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1757	1			T43	1		T70	3		T108	26
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1785	1			T169	1		T4	4		T70	2
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1763	1			T87	1		T48	1		T65	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1718	1			T65	2		T170	3		T108	12
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1764	1			T3	1		T43	1		T123	2
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1614	1			T108	19		T168	7		T195	6
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1569	1			T120	1		T108	26		T168	5
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1639	1			T43	1		T120	1		T108	16
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1545	1			T108	19		T168	9		T423	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	5801	1			T42	1		T28	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	6842	1			T34	1		T87	1		T37	2
pkt_types[PidTypeOutToken]	endpoints[0x2]	8251	1			T34	1		T35	1		T36	11
pkt_types[PidTypeOutToken]	endpoints[0x3]	4800	1			T34	1		T88	1		T419	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4070	1			T32	1		T34	1		T87	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	6886	1			T1	1		T30	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	7417	1			T34	1		T37	4		T74	11
pkt_types[PidTypeOutToken]	endpoints[0x7]	5599	1			T34	1		T37	1		T162	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	4834	1			T29	11		T34	1		T87	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6189	1			T34	1		T37	2		T38	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4799	1			T34	1		T37	1		T65	2
pkt_types[PidTypeOutToken]	endpoints[0xb]	4862	1			T43	1		T34	1		T37	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1073	1			T108	23		T121	29		T122	23
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1105	1			T43	2		T108	15		T121	24
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1017	1			T108	19		T121	34		T122	20
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1069	1			T43	1		T120	1		T108	19
pkt_types[PidTypeInToken]	endpoints[0x0]	4367	1			T34	1		T24	1		T4	9
pkt_types[PidTypeInToken]	endpoints[0x1]	5196	1			T34	1		T87	3		T37	2
pkt_types[PidTypeInToken]	endpoints[0x2]	4351	1			T43	1		T34	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5029	1			T43	1		T34	1		T37	1
pkt_types[PidTypeInToken]	endpoints[0x4]	5495	1			T32	1		T34	1		T37	3
pkt_types[PidTypeInToken]	endpoints[0x5]	5079	1			T30	1		T31	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4969	1			T34	1		T37	3		T4	9
pkt_types[PidTypeInToken]	endpoints[0x7]	4497	1			T34	1		T37	2		T162	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4895	1			T34	1		T37	2		T23	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4930	1			T34	1		T37	2		T38	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4633	1			T43	1		T34	1		T37	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4494	1			T43	1		T34	1		T123	9