Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90870	1			T1	6		T2	3		T3	7
all_values[1]	90870	1			T1	6		T2	3		T3	7
all_values[2]	90870	1			T1	6		T2	3		T3	7
all_values[3]	90870	1			T1	6		T2	3		T3	7
all_values[4]	90870	1			T1	6		T2	3		T3	7
all_values[5]	90870	1			T1	6		T2	3		T3	7
all_values[6]	90870	1			T1	6		T2	3		T3	7
all_values[7]	90870	1			T1	6		T2	3		T3	7
all_values[8]	90870	1			T1	6		T2	3		T3	7
all_values[9]	90870	1			T1	6		T2	3		T3	7
all_values[10]	90870	1			T1	6		T2	3		T3	7
all_values[11]	90870	1			T1	6		T2	3		T3	7
all_values[12]	90870	1			T1	6		T2	3		T3	7
all_values[13]	90870	1			T1	6		T2	3		T3	7
all_values[14]	90870	1			T1	6		T2	3		T3	7
all_values[15]	90870	1			T1	6		T2	3		T3	7
all_values[16]	90870	1			T1	6		T2	3		T3	7
all_values[17]	90870	1			T1	6		T2	3		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2898449

1

T1

189

T2

94

T3

219

auto[1]

9391

1

T1

3

T2

2

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431992

1

T1

177

T2

85

T3

210

auto[1]

475848

1

T1

15

T2

11

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62789	1			T1	3		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	24912	1			T1	3		T28	1		T31	2
all_values[0]	auto[1]	auto[0]	3063	1			T24	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	106	1			T381	1		T382	1		T383	1
all_values[1]	auto[0]	auto[0]	86513	1			T1	6		T2	3		T3	7
all_values[1]	auto[0]	auto[1]	2966	1			T29	2		T30	2		T35	1
all_values[1]	auto[1]	auto[0]	518	1			T32	2		T36	2		T7	1
all_values[1]	auto[1]	auto[1]	873	1			T32	12		T36	1		T7	1
all_values[2]	auto[0]	auto[0]	4333	1			T1	5		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	86288	1			T1	1		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	132	1			T41	1		T66	1		T67	1
all_values[2]	auto[1]	auto[1]	117	1			T41	1		T66	1		T67	1
all_values[3]	auto[0]	auto[0]	88996	1			T1	6		T2	3		T3	7
all_values[3]	auto[0]	auto[1]	304	1			T49	1		T68	1		T69	1
all_values[3]	auto[1]	auto[0]	1510	1			T49	1427		T210	2		T211	6
all_values[3]	auto[1]	auto[1]	60	1			T49	1		T211	1		T212	3
all_values[4]	auto[0]	auto[0]	4322	1			T1	5		T2	1		T3	6
all_values[4]	auto[0]	auto[1]	86390	1			T1	1		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	100	1			T48	1		T210	2		T211	2
all_values[4]	auto[1]	auto[1]	58	1			T48	1		T210	1		T212	1
all_values[5]	auto[0]	auto[0]	90356	1			T1	6		T2	3		T3	7
all_values[5]	auto[0]	auto[1]	368	1			T7	1		T8	1		T62	1
all_values[5]	auto[1]	auto[0]	89	1			T210	4		T211	1		T212	1
all_values[5]	auto[1]	auto[1]	57	1			T211	3		T281	1		T289	1
all_values[6]	auto[0]	auto[0]	90438	1			T1	6		T2	3		T3	7
all_values[6]	auto[0]	auto[1]	207	1			T8	1		T68	1		T70	1
all_values[6]	auto[1]	auto[0]	97	1			T210	6		T211	3		T212	2
all_values[6]	auto[1]	auto[1]	128	1			T71	1		T72	1		T73	1
all_values[7]	auto[0]	auto[0]	35669	1			T2	3		T3	5		T41	2
all_values[7]	auto[0]	auto[1]	55048	1			T1	6		T3	2		T28	4
all_values[7]	auto[1]	auto[0]	112	1			T52	2		T210	2		T211	1
all_values[7]	auto[1]	auto[1]	41	1			T52	1		T210	1		T211	1
all_values[8]	auto[0]	auto[0]	89994	1			T1	6		T2	3		T3	7
all_values[8]	auto[0]	auto[1]	209	1			T58	2		T300	2		T355	2
all_values[8]	auto[1]	auto[0]	596	1			T56	10		T54	10		T57	10
all_values[8]	auto[1]	auto[1]	71	1			T54	1		T57	1		T59	1
all_values[9]	auto[0]	auto[0]	90618	1			T1	6		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	56	1			T210	1		T211	2		T212	2
all_values[9]	auto[1]	auto[0]	125	1			T3	3		T64	3		T65	3
all_values[9]	auto[1]	auto[1]	71	1			T3	2		T64	2		T65	2
all_values[10]	auto[0]	auto[0]	90324	1			T1	6		T2	3		T3	7
all_values[10]	auto[0]	auto[1]	382	1			T30	1		T37	2		T40	1
all_values[10]	auto[1]	auto[0]	77	1			T211	2		T212	1		T281	1
all_values[10]	auto[1]	auto[1]	87	1			T210	3		T211	3		T212	2
all_values[11]	auto[0]	auto[0]	90018	1			T1	6		T2	2		T3	7
all_values[11]	auto[0]	auto[1]	602	1			T2	1		T34	4		T38	4
all_values[11]	auto[1]	auto[0]	140	1			T74	1		T75	1		T76	1
all_values[11]	auto[1]	auto[1]	110	1			T74	1		T75	1		T76	1
all_values[12]	auto[0]	auto[0]	90547	1			T1	6		T2	3		T3	7
all_values[12]	auto[0]	auto[1]	159	1			T79	3		T81	1		T82	1
all_values[12]	auto[1]	auto[0]	105	1			T77	2		T78	2		T80	2
all_values[12]	auto[1]	auto[1]	59	1			T77	1		T78	1		T80	1
all_values[13]	auto[0]	auto[0]	90542	1			T1	6		T2	1		T3	7
all_values[13]	auto[0]	auto[1]	77	1			T81	1		T82	1		T85	1
all_values[13]	auto[1]	auto[0]	148	1			T2	1		T83	1		T84	1
all_values[13]	auto[1]	auto[1]	103	1			T2	1		T83	1		T84	1
all_values[14]	auto[0]	auto[0]	18349	1			T1	6		T2	3		T3	7
all_values[14]	auto[0]	auto[1]	72361	1			T41	1		T7	2		T8	2
all_values[14]	auto[1]	auto[0]	95	1			T210	2		T211	4		T281	2
all_values[14]	auto[1]	auto[1]	65	1			T210	4		T211	1		T212	3
all_values[15]	auto[0]	auto[0]	4375	1			T1	5		T2	1		T3	6
all_values[15]	auto[0]	auto[1]	86343	1			T1	1		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	87	1			T210	1		T211	4		T281	1
all_values[15]	auto[1]	auto[1]	65	1			T210	2		T211	2		T212	4
all_values[16]	auto[0]	auto[0]	89875	1			T1	6		T2	3		T3	7
all_values[16]	auto[0]	auto[1]	839	1			T30	1		T17	1		T19	1
all_values[16]	auto[1]	auto[0]	85	1			T34	4		T38	4		T22	4
all_values[16]	auto[1]	auto[1]	71	1			T34	4		T38	4		T22	4
all_values[17]	auto[0]	auto[0]	34566	1			T1	1		T87	2		T88	2
all_values[17]	auto[0]	auto[1]	56134	1			T1	2		T2	3		T3	7
all_values[17]	auto[1]	auto[0]	109	1			T1	2		T60	2		T61	2
all_values[17]	auto[1]	auto[1]	61	1			T1	1		T60	1		T61	1