Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 98.23 96.03 97.44 94.92 98.42 98.21 98.64


Total tests in report: 3837
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.85 66.85 88.14 88.14 71.08 71.08 60.55 60.55 47.46 47.46 83.53 83.53 91.07 91.07 26.15 26.15 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2552505539
72.86 6.00 89.39 1.25 76.12 5.04 84.86 24.31 47.46 0.00 85.69 2.16 91.47 0.40 35.02 8.87 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2906997548
76.15 3.29 92.02 2.62 82.94 6.83 86.03 1.17 47.46 0.00 93.55 7.86 91.47 0.00 39.55 4.52 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.4291916491
79.25 3.10 93.69 1.67 85.20 2.26 88.06 2.03 59.32 11.86 95.01 1.46 93.45 1.98 40.00 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3367900587
81.49 2.24 94.39 0.70 85.32 0.12 89.98 1.92 59.32 0.00 95.01 0.00 93.65 0.20 52.76 12.76 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.110890249
83.28 1.79 94.62 0.23 86.25 0.93 89.98 0.00 66.10 6.78 95.34 0.33 93.65 0.00 57.01 4.25 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.361241366
84.42 1.14 94.87 0.25 86.51 0.26 90.41 0.43 72.88 6.78 95.51 0.17 93.65 0.00 57.10 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.2003470719
85.52 1.10 95.97 1.10 86.92 0.40 91.26 0.85 72.88 0.00 95.55 0.04 96.23 2.58 59.82 2.71 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2627243314
86.39 0.87 96.08 0.11 87.06 0.14 91.47 0.21 77.97 5.08 95.72 0.17 96.23 0.00 60.18 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.4222757516
87.26 0.87 96.16 0.08 87.82 0.76 91.47 0.00 77.97 0.00 95.80 0.08 96.23 0.00 65.34 5.16 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.3847419191
88.05 0.80 96.65 0.49 88.46 0.64 91.68 0.21 81.36 3.39 96.01 0.21 96.23 0.00 65.97 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.2624253728
88.73 0.67 96.67 0.02 88.53 0.07 95.52 3.84 81.36 0.00 96.05 0.04 96.43 0.20 66.52 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2580460594
89.27 0.55 96.84 0.17 88.63 0.10 95.52 0.00 84.75 3.39 96.21 0.17 96.43 0.00 66.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.654709199
89.76 0.48 96.84 0.00 88.63 0.00 95.52 0.00 88.14 3.39 96.21 0.00 96.43 0.00 66.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/313.usbdev_tx_rx_disruption.3670197845
90.20 0.45 97.59 0.74 89.84 1.21 95.52 0.00 88.14 0.00 97.38 1.16 96.43 0.00 66.52 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.4177780673
90.64 0.44 97.59 0.00 89.84 0.00 95.95 0.43 88.14 0.00 97.38 0.00 96.43 0.00 69.14 2.62 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.3565464495
90.97 0.33 97.64 0.06 91.18 1.33 95.95 0.00 88.14 0.00 97.46 0.08 96.63 0.20 69.77 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.4016943049
91.29 0.33 97.87 0.23 91.86 0.69 96.27 0.32 88.14 0.00 97.88 0.42 96.63 0.00 70.41 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.3575196342
91.56 0.26 97.87 0.00 91.91 0.05 96.38 0.11 89.83 1.69 97.88 0.00 96.63 0.00 70.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_tx_rx_disruption.1998469771
91.82 0.26 97.89 0.02 91.91 0.00 96.38 0.00 91.53 1.69 97.92 0.04 96.63 0.00 70.50 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.2510183664
92.08 0.26 97.91 0.02 92.10 0.19 96.38 0.00 91.53 0.00 97.96 0.04 96.63 0.00 72.04 1.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.3693381592
92.33 0.25 97.93 0.02 92.13 0.02 96.38 0.00 93.22 1.69 98.00 0.04 96.63 0.00 72.04 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/126.usbdev_tx_rx_disruption.3096379358
92.57 0.24 97.93 0.00 92.13 0.00 96.38 0.00 94.92 1.69 98.00 0.00 96.63 0.00 72.04 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_resume.4120775692
92.81 0.24 98.02 0.10 92.72 0.59 96.38 0.00 94.92 0.00 98.17 0.17 96.63 0.00 72.85 0.81 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.4111098806
93.01 0.20 98.02 0.00 92.86 0.14 96.38 0.00 94.92 0.00 98.17 0.00 96.63 0.00 74.12 1.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2752563729
93.21 0.20 98.02 0.00 92.86 0.00 96.38 0.00 94.92 0.00 98.17 0.00 98.02 1.39 74.12 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.2047196122
93.38 0.16 98.02 0.00 93.74 0.88 96.38 0.00 94.92 0.00 98.17 0.00 98.02 0.00 74.39 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.601679073
93.53 0.16 98.02 0.00 93.96 0.21 96.59 0.21 94.92 0.00 98.21 0.04 98.02 0.00 75.02 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.3587239494
93.68 0.14 98.02 0.00 93.96 0.00 96.59 0.00 94.92 0.00 98.21 0.00 98.02 0.00 76.02 1.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1659735163
93.80 0.13 98.02 0.00 94.01 0.05 96.80 0.21 94.92 0.00 98.21 0.00 98.02 0.00 76.65 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1087769676
93.92 0.12 98.02 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.21 0.00 98.02 0.00 77.47 0.81 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.3593338322
94.03 0.11 98.02 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.21 0.00 98.21 0.20 78.01 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.3107770205
94.13 0.10 98.02 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.21 0.00 98.21 0.00 78.73 0.72 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/146.usbdev_endpoint_types.272005918
94.23 0.10 98.02 0.00 94.01 0.00 96.80 0.00 94.92 0.00 98.21 0.00 98.21 0.00 79.46 0.72 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.3175186050
94.33 0.10 98.02 0.00 94.05 0.05 97.01 0.21 94.92 0.00 98.21 0.00 98.21 0.00 79.91 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.1487876111
94.44 0.10 98.02 0.00 94.10 0.05 97.23 0.21 94.92 0.00 98.21 0.00 98.21 0.00 80.36 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3906937987
94.53 0.09 98.02 0.00 94.12 0.02 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 81.00 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/18.usbdev_device_address.4216678745
94.62 0.09 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 81.63 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.3275332455
94.71 0.09 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 82.26 0.63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/8.usbdev_data_toggle_restore.2732490663
94.79 0.08 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 82.81 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/151.usbdev_endpoint_types.1297905697
94.87 0.08 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 83.35 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/153.usbdev_endpoint_types.334469945
94.94 0.08 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 83.89 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_types.415059828
95.02 0.08 98.02 0.00 94.12 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 84.43 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.2773599344
95.09 0.07 98.02 0.00 94.46 0.33 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 84.62 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.1447838366
95.16 0.06 98.02 0.00 94.46 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 85.07 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/162.usbdev_endpoint_types.3685601407
95.22 0.06 98.02 0.00 94.46 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 85.52 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.2012056257
95.29 0.06 98.02 0.00 94.46 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 85.97 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/6.usbdev_device_address.2822235403
95.35 0.06 98.02 0.00 94.46 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 86.43 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.1534123773
95.42 0.06 98.02 0.00 94.46 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 86.88 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.957743946
95.48 0.06 98.02 0.00 94.53 0.07 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 87.24 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.340444768
95.53 0.05 98.02 0.00 94.53 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 87.60 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.3034695357
95.58 0.05 98.02 0.00 94.53 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 87.96 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.781563017
95.64 0.05 98.02 0.00 94.53 0.00 97.23 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.33 0.36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.222396559
95.68 0.05 98.08 0.06 94.60 0.07 97.44 0.21 94.92 0.00 98.21 0.00 98.21 0.00 88.33 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3056086602
95.73 0.04 98.08 0.00 94.62 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.60 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.997795229
95.77 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.87 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.211984058
95.80 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.14 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1497541201
95.84 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.41 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/10.usbdev_min_inter_pkt_delay.3903442999
95.88 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.68 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.1735002451
95.92 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.95 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/13.usbdev_device_address.3476420182
95.96 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.23 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/179.usbdev_endpoint_types.4126325202
96.00 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.50 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.1715192435
96.04 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.77 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.362312609
96.08 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.04 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.1784391903
96.11 0.04 98.08 0.00 94.62 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.31 0.27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.1887393954
96.15 0.04 98.14 0.06 94.65 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.49 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.845163122
96.19 0.04 98.19 0.06 94.67 0.02 97.44 0.00 94.92 0.00 98.29 0.08 98.21 0.00 91.58 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/12.usbdev_fifo_levels.1722801328
96.22 0.03 98.19 0.00 94.86 0.19 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 91.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2042707210
96.24 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 91.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.848971242
96.27 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 91.95 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2713400125
96.29 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 92.13 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.1004935201
96.32 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 92.31 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/112.usbdev_endpoint_types.3564598771
96.34 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 92.49 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/149.usbdev_endpoint_types.1973465611
96.37 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 92.67 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.1833202775
96.40 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 92.85 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.2085418536
96.42 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 93.03 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.4179422406
96.45 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 93.21 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.2508786557
96.47 0.03 98.19 0.00 94.86 0.00 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 93.39 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.3025978725
96.50 0.02 98.21 0.02 94.96 0.10 97.44 0.00 94.92 0.00 98.34 0.04 98.21 0.00 93.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_disconnects.1685841800
96.52 0.02 98.23 0.02 94.96 0.00 97.44 0.00 94.92 0.00 98.38 0.04 98.21 0.00 93.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/13.usbdev_fifo_levels.1587449010
96.54 0.02 98.23 0.00 95.10 0.14 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.976035802
96.56 0.02 98.23 0.00 95.15 0.05 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3038540197
96.57 0.02 98.23 0.00 95.27 0.12 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/6.usbdev_stress_usb_traffic.2326827804
96.59 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.67 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.525961112
96.60 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.76 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.1687851502
96.61 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.85 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.2843512372
96.63 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 93.94 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.3776028496
96.64 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.03 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.4074508665
96.65 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.12 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.2180306099
96.67 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.21 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/10.usbdev_fifo_levels.1688184647
96.68 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.30 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/101.usbdev_fifo_levels.1518577790
96.69 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.39 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.1814050211
96.70 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/104.usbdev_fifo_levels.2159754069
96.72 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/108.usbdev_fifo_levels.517268804
96.73 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.66 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.1107839288
96.74 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.75 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/109.usbdev_fifo_levels.2385453364
96.76 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.84 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/112.usbdev_fifo_levels.1926892107
96.77 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 94.93 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/114.usbdev_fifo_levels.470869161
96.78 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.02 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/116.usbdev_fifo_levels.4128429472
96.79 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.11 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/117.usbdev_fifo_levels.3254672529
96.81 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.20 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/118.usbdev_fifo_levels.3833410503
96.82 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.3095195306
96.83 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/122.usbdev_fifo_levels.2583320646
96.85 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.2723100721
96.86 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/123.usbdev_fifo_levels.2696070649
96.87 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.66 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.3979191462
96.88 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.75 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/125.usbdev_fifo_levels.1259872983
96.90 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.84 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/130.usbdev_fifo_levels.3020068871
96.91 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 95.93 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/132.usbdev_endpoint_types.1598265811
96.92 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.02 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/135.usbdev_fifo_levels.744681587
96.94 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.11 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/137.usbdev_fifo_levels.418260371
96.95 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.20 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_types.2770633813
96.96 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/14.usbdev_phy_config_usb_ref_disable.2324935992
96.98 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/140.usbdev_fifo_levels.2656774122
96.99 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.47 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/142.usbdev_fifo_levels.2387424788
97.00 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.56 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/145.usbdev_endpoint_types.1909051370
97.01 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.65 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/145.usbdev_fifo_levels.3986814838
97.03 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.74 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/146.usbdev_fifo_levels.2139030628
97.04 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.83 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/148.usbdev_fifo_levels.3058480034
97.05 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 96.92 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/150.usbdev_endpoint_types.4109327543
97.07 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.01 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/152.usbdev_fifo_levels.1589364729
97.08 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.10 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/16.usbdev_fifo_levels.134391915
97.09 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.19 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/17.usbdev_spurious_pids_ignored.3176026587
97.10 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/189.usbdev_endpoint_types.2899122784
97.12 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/20.usbdev_fifo_levels.3210714829
97.13 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.47 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/22.usbdev_fifo_levels.18921754
97.14 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.56 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/25.usbdev_fifo_levels.3932415069
97.16 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.65 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/40.usbdev_fifo_levels.1415036640
97.17 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.74 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/42.usbdev_fifo_levels.2817165983
97.18 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.83 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/46.usbdev_fifo_levels.2136749984
97.20 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 97.92 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/47.usbdev_fifo_levels.3266979465
97.21 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.01 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.460962687
97.22 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.10 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.3211010437
97.23 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.19 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/60.usbdev_fifo_levels.3113371915
97.25 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.28 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/62.usbdev_fifo_levels.2284495566
97.26 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.37 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/65.usbdev_fifo_levels.2746506135
97.27 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.46 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.396912739
97.29 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.55 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/96.usbdev_fifo_levels.890015031
97.30 0.01 98.23 0.00 95.27 0.00 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.64 0.09 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/99.usbdev_fifo_levels.548229962
97.31 0.01 98.23 0.00 95.31 0.05 97.44 0.00 94.92 0.00 98.42 0.04 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2253937180
97.32 0.01 98.23 0.00 95.39 0.07 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.1706586573
97.33 0.01 98.23 0.00 95.46 0.07 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/4.usbdev_phy_pins_sense.3922167086
97.34 0.01 98.23 0.00 95.50 0.05 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.2156130806
97.35 0.01 98.23 0.00 95.55 0.05 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3239183383
97.35 0.01 98.23 0.00 95.60 0.05 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.93150461
97.36 0.01 98.23 0.00 95.65 0.05 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.3760903834
97.36 0.01 98.23 0.00 95.67 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.2603298368
97.37 0.01 98.23 0.00 95.69 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.4132957387
97.37 0.01 98.23 0.00 95.72 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.1612618150
97.37 0.01 98.23 0.00 95.74 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2858460769
97.38 0.01 98.23 0.00 95.77 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/10.usbdev_nak_trans.2415651260
97.38 0.01 98.23 0.00 95.79 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/11.usbdev_nak_trans.164941196
97.38 0.01 98.23 0.00 95.81 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.3741264332
97.39 0.01 98.23 0.00 95.84 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/12.usbdev_nak_trans.445793245
97.39 0.01 98.23 0.00 95.86 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/14.usbdev_nak_trans.2069198934
97.39 0.01 98.23 0.00 95.88 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.2970240684
97.40 0.01 98.23 0.00 95.91 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.776032292
97.40 0.01 98.23 0.00 95.93 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_stress_usb_traffic.1459094079
97.40 0.01 98.23 0.00 95.96 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/33.usbdev_nak_trans.4200289886
97.41 0.01 98.23 0.00 95.98 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/34.usbdev_nak_trans.107624728
97.41 0.01 98.23 0.00 96.00 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/4.usbdev_stress_usb_traffic.4269871627
97.41 0.01 98.23 0.00 96.03 0.02 97.44 0.00 94.92 0.00 98.42 0.00 98.21 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/44.usbdev_nak_trans.33468298

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2947671621
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3506358238
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2340593836
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.53885197
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.515537649
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1876665003
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1944164648
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.2512082972
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.1282410571
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2669553925
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2209585316
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2327610107
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.3163289897
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.3097197011
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2273424943
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.3668513005
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.391486210
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3636510155
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.3540275031
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4279352018
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2845838507
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.2079098164
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.287849129
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.2963997114
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2808791125
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1557857608
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.644412855
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.900621085
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.2345623409
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.435735744
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1548693675
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.991781852
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.73306004
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1220226013
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.3999250805
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.2410033956
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2104451166
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.1897035167
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.3612387871
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3806275700
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.4243436004
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.3282011634
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2803473101
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.2099690782
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2683737499
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4133530940
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.2557067587
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3872692686
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.151936164
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.3589130069
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2861985861
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.3354462570
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.506866897
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3487995306
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.2575919860
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.3486724697
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2011083353
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.1445031271
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.1937261914
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1383302213
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.3002778308
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.2786918789
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2912285225
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.3690004907
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3554470677
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1302597572
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.1409986817
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.1463597747
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.4267562042
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1730567100
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2852841019
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.855361621
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.3648225872
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2604420381
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.2315021762
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3777258499
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.286737951
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.3434980552
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.2798581083
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.368600118
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.2721676334
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.1915438609
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.2876292537
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.2449486760
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1990910653
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1310789869
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4085619182
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1332273118
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2073077768
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2575045151
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2485909565
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1827529706
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.976627683
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2806402632
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.494631906
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.3035532021
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.2344854577
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.1281380648
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.3041716752
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.58419699
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.2137728240
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.499992524
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.1683219474
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.952175644
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.2931662939
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2494524323
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3007514320
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3035678150
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.42292106
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.161431398
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.3269779112
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.3216595327
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.704211803
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3018842149
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3787101030
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.43117542
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.1489154506
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.3482663917
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.1231443996
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.3384095411
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.1716009281
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.2303812523
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.3503272367
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.1182891217
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.99544351
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3896626937
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.2183223602
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.1457344819
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.850820900
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.2625672944
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.2625587408
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2528856125
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.3757306208
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3706238074
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2899518089
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.3146097121
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.36705334
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2010277527
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.1393273645
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.2193339704
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3029359483
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.2318798410
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2031113823
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2950265373
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.3961097785
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/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_out_transaction.2541447189
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.467619469
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.1249636039
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.1726608934
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_in_transaction.2266635328
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_out_transaction.168402485
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_nak_trans.3251152675
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_out_iso.199002321
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_out_stall.1298148322
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_out_trans_nak.3230236890
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_pending_in_trans.1310990147
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_pinflip.1089339430
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_usb_ref_disable.17387171
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.727346097
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_buffer.1135420214
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.1393692331
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_sent.765872768
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_resets.3228003125
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_rand_suspends.3250225245
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_in_transaction.1554225565
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_out_transaction.4109368864
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.1161334406
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_rx_crc_err.787367992
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_rx_full.3153713088
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_setup_stage.1650452613
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_setup_trans_ignored.4016860685
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_smoke.1361764723
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_spurious_pids_ignored.1263916152
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_stall_priority_over_nak.2869172552
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_stall_trans.3960642657
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_stream_len_max.2051343453
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_streaming_out.3247364190
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_stress_usb_traffic.2408991348
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_timeout_missing_host_handshake.2247324619
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/9.usbdev_tx_rx_disruption.587376990
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.1708774742
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/90.usbdev_fifo_levels.618562577
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.3870235163
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.3299287003
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/91.usbdev_fifo_levels.1930064631
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.902891048
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/92.usbdev_fifo_levels.3083389095
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.1984076014
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.2162346481
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/93.usbdev_fifo_levels.1843197787
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.1626933043
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.14942267
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/94.usbdev_fifo_levels.3060445467
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.2244801341
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/95.usbdev_fifo_levels.4281917890
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.1829903685
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.1290850874
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.277085643
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1026748153
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/97.usbdev_fifo_levels.2849682961
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.422132280
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.3385064229
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/98.usbdev_fifo_levels.150796304
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.208076018
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.117289501
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.662415997



Total test records in report: 3837
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.2156130806 Oct 02 10:57:58 PM UTC 24 Oct 02 10:58:01 PM UTC 24 151958543 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1087769676 Oct 02 10:57:58 PM UTC 24 Oct 02 10:58:01 PM UTC 24 160384429 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2042707210 Oct 02 10:57:58 PM UTC 24 Oct 02 10:58:01 PM UTC 24 132221070 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.2763617427 Oct 02 10:57:58 PM UTC 24 Oct 02 10:58:01 PM UTC 24 176492482 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.2855445545 Oct 02 10:57:59 PM UTC 24 Oct 02 10:58:03 PM UTC 24 452261895 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.1487876111 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:04 PM UTC 24 158358312 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_enable.2506232791 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:04 PM UTC 24 32954959 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.1989650798 Oct 02 10:58:01 PM UTC 24 Oct 02 10:58:04 PM UTC 24 810952880 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.1687851502 Oct 02 10:58:03 PM UTC 24 Oct 02 10:58:06 PM UTC 24 157537418 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2552505539 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:07 PM UTC 24 1015555448 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.2457997599 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:07 PM UTC 24 975268658 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.4291916491 Oct 02 10:58:03 PM UTC 24 Oct 02 10:58:07 PM UTC 24 733457303 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2906997548 Oct 02 10:58:03 PM UTC 24 Oct 02 10:58:08 PM UTC 24 208183487 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.3972413322 Oct 02 10:58:06 PM UTC 24 Oct 02 10:58:08 PM UTC 24 144603353 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.4111098806 Oct 02 10:58:05 PM UTC 24 Oct 02 10:58:08 PM UTC 24 485102167 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.4284256414 Oct 02 10:58:06 PM UTC 24 Oct 02 10:58:08 PM UTC 24 239380475 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.4069709054 Oct 02 10:58:07 PM UTC 24 Oct 02 10:58:09 PM UTC 24 212289552 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.2751103603 Oct 02 10:58:08 PM UTC 24 Oct 02 10:58:10 PM UTC 24 162419114 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3239183383 Oct 02 10:58:08 PM UTC 24 Oct 02 10:58:11 PM UTC 24 235135624 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.2709116466 Oct 02 10:58:08 PM UTC 24 Oct 02 10:58:11 PM UTC 24 500393064 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.887196617 Oct 02 10:58:09 PM UTC 24 Oct 02 10:58:12 PM UTC 24 190762275 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.3564441557 Oct 02 10:58:09 PM UTC 24 Oct 02 10:58:12 PM UTC 24 245095239 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.1556695637 Oct 02 10:58:01 PM UTC 24 Oct 02 10:58:12 PM UTC 24 609539389 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.2448871785 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:13 PM UTC 24 1093403234 ps
T557 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.366349098 Oct 02 10:58:12 PM UTC 24 Oct 02 10:58:14 PM UTC 24 153542353 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.1470636456 Oct 02 10:58:12 PM UTC 24 Oct 02 10:58:14 PM UTC 24 185025215 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3367900587 Oct 02 10:57:56 PM UTC 24 Oct 02 10:58:14 PM UTC 24 10594068608 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.2843512372 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:15 PM UTC 24 187849542 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.1251806073 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:15 PM UTC 24 149335540 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.845163122 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:15 PM UTC 24 202578970 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.1873249926 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:15 PM UTC 24 182414729 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.1301699579 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:15 PM UTC 24 219068906 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1461232507 Oct 02 10:58:13 PM UTC 24 Oct 02 10:58:16 PM UTC 24 515486616 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1941221755 Oct 02 10:58:14 PM UTC 24 Oct 02 10:58:17 PM UTC 24 196648296 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.705744145 Oct 02 10:57:57 PM UTC 24 Oct 02 10:58:18 PM UTC 24 14712450904 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.494641771 Oct 02 10:58:15 PM UTC 24 Oct 02 10:58:18 PM UTC 24 314027354 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.3575196342 Oct 02 10:58:15 PM UTC 24 Oct 02 10:58:18 PM UTC 24 237628894 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.3440336698 Oct 02 10:58:15 PM UTC 24 Oct 02 10:58:18 PM UTC 24 268322758 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.934919038 Oct 02 10:58:33 PM UTC 24 Oct 02 10:58:36 PM UTC 24 290214677 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.654709199 Oct 02 10:58:15 PM UTC 24 Oct 02 10:58:18 PM UTC 24 302923077 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2253937180 Oct 02 10:58:16 PM UTC 24 Oct 02 10:58:18 PM UTC 24 140805272 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.2786464051 Oct 02 10:58:17 PM UTC 24 Oct 02 10:58:19 PM UTC 24 33756363 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1914879807 Oct 02 10:58:16 PM UTC 24 Oct 02 10:58:19 PM UTC 24 217778655 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.173346318 Oct 02 10:58:17 PM UTC 24 Oct 02 10:58:19 PM UTC 24 179111316 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1497541201 Oct 02 10:58:17 PM UTC 24 Oct 02 10:58:20 PM UTC 24 252923885 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.227285060 Oct 02 10:58:18 PM UTC 24 Oct 02 10:58:20 PM UTC 24 206650516 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3038540197 Oct 02 10:58:04 PM UTC 24 Oct 02 10:58:20 PM UTC 24 4166532471 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.4099023580 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:21 PM UTC 24 179456588 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3906937987 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:21 PM UTC 24 131137500 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.93150461 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:22 PM UTC 24 165514031 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.4013374912 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:22 PM UTC 24 333160724 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.2635290045 Oct 02 10:58:20 PM UTC 24 Oct 02 10:58:23 PM UTC 24 209663023 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.3728744032 Oct 02 10:58:20 PM UTC 24 Oct 02 10:58:23 PM UTC 24 167739549 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.3776028496 Oct 02 10:58:20 PM UTC 24 Oct 02 10:58:23 PM UTC 24 192579187 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.4074508665 Oct 02 10:58:22 PM UTC 24 Oct 02 10:58:24 PM UTC 24 157259512 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.340444768 Oct 02 10:58:20 PM UTC 24 Oct 02 10:58:24 PM UTC 24 412067444 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.2759633163 Oct 02 10:58:22 PM UTC 24 Oct 02 10:58:25 PM UTC 24 204031022 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.584332080 Oct 02 10:58:09 PM UTC 24 Oct 02 10:58:25 PM UTC 24 9135505107 ps
T524 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.2703721773 Oct 02 10:58:23 PM UTC 24 Oct 02 10:58:25 PM UTC 24 173068837 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.970866516 Oct 02 10:58:31 PM UTC 24 Oct 02 10:58:36 PM UTC 24 751151663 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3056086602 Oct 02 10:58:25 PM UTC 24 Oct 02 10:58:28 PM UTC 24 39728006 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.1185218438 Oct 02 10:58:24 PM UTC 24 Oct 02 10:58:28 PM UTC 24 483874694 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2580460594 Oct 02 10:58:25 PM UTC 24 Oct 02 10:58:29 PM UTC 24 678431799 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.1547742607 Oct 02 10:58:23 PM UTC 24 Oct 02 10:58:29 PM UTC 24 1009500824 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.2439477825 Oct 02 10:58:27 PM UTC 24 Oct 02 10:58:29 PM UTC 24 155321136 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.383656448 Oct 02 10:58:27 PM UTC 24 Oct 02 10:58:29 PM UTC 24 217327562 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.1706586573 Oct 02 10:58:28 PM UTC 24 Oct 02 10:58:30 PM UTC 24 150810479 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.3097921533 Oct 02 10:58:11 PM UTC 24 Oct 02 10:58:31 PM UTC 24 2612063161 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.3546226640 Oct 02 10:58:29 PM UTC 24 Oct 02 10:58:31 PM UTC 24 144786146 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.296944230 Oct 02 10:58:29 PM UTC 24 Oct 02 10:58:32 PM UTC 24 478813642 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.3102464693 Oct 02 10:58:30 PM UTC 24 Oct 02 10:58:33 PM UTC 24 165671011 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.1004935201 Oct 02 10:58:29 PM UTC 24 Oct 02 10:58:33 PM UTC 24 881001437 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_enable.3126692554 Oct 02 10:58:31 PM UTC 24 Oct 02 10:58:33 PM UTC 24 33705962 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.1618140638 Oct 02 10:58:30 PM UTC 24 Oct 02 10:58:34 PM UTC 24 572833086 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.2710580291 Oct 02 10:58:32 PM UTC 24 Oct 02 10:58:34 PM UTC 24 186376493 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1659735163 Oct 02 10:58:31 PM UTC 24 Oct 02 10:58:35 PM UTC 24 554647304 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.979894653 Oct 02 10:58:09 PM UTC 24 Oct 02 10:58:36 PM UTC 24 2595653228 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.145357031 Oct 02 10:58:23 PM UTC 24 Oct 02 10:58:36 PM UTC 24 1666702775 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.2029041802 Oct 02 10:58:35 PM UTC 24 Oct 02 10:58:38 PM UTC 24 198853786 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.2559060101 Oct 02 10:58:35 PM UTC 24 Oct 02 10:58:38 PM UTC 24 176203374 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.1447838366 Oct 02 10:58:10 PM UTC 24 Oct 02 10:58:38 PM UTC 24 2618789163 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.355174966 Oct 02 10:58:35 PM UTC 24 Oct 02 10:58:38 PM UTC 24 239141661 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.4223724299 Oct 02 10:58:25 PM UTC 24 Oct 02 10:58:38 PM UTC 24 4108302031 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.4132957387 Oct 02 10:58:05 PM UTC 24 Oct 02 10:58:39 PM UTC 24 3513504480 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.1623416395 Oct 02 10:58:37 PM UTC 24 Oct 02 10:58:39 PM UTC 24 211096918 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.361241366 Oct 02 10:58:09 PM UTC 24 Oct 02 10:58:41 PM UTC 24 4018836458 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.2165611314 Oct 02 10:58:22 PM UTC 24 Oct 02 10:58:41 PM UTC 24 2331025239 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.3932214364 Oct 02 10:58:39 PM UTC 24 Oct 02 10:58:41 PM UTC 24 243148894 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.701008590 Oct 02 10:58:39 PM UTC 24 Oct 02 10:58:42 PM UTC 24 188524843 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.1294157358 Oct 02 10:58:40 PM UTC 24 Oct 02 10:58:43 PM UTC 24 157012574 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.1520947814 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:44 PM UTC 24 5557323755 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2858460769 Oct 02 10:58:42 PM UTC 24 Oct 02 10:58:44 PM UTC 24 176234922 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.1578770618 Oct 02 10:58:42 PM UTC 24 Oct 02 10:58:44 PM UTC 24 161365664 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.3996783065 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:44 PM UTC 24 3227179145 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.2431806521 Oct 02 10:58:43 PM UTC 24 Oct 02 10:58:45 PM UTC 24 140177457 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.4030571519 Oct 02 10:58:43 PM UTC 24 Oct 02 10:58:45 PM UTC 24 155516308 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.2824327662 Oct 02 10:58:44 PM UTC 24 Oct 02 10:58:46 PM UTC 24 153160120 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.408543139 Oct 02 10:58:44 PM UTC 24 Oct 02 10:58:46 PM UTC 24 160389778 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.4177780673 Oct 02 10:58:45 PM UTC 24 Oct 02 10:58:47 PM UTC 24 49528027 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.2966909686 Oct 02 10:58:45 PM UTC 24 Oct 02 10:58:47 PM UTC 24 211851423 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.291176275 Oct 02 10:58:45 PM UTC 24 Oct 02 10:58:47 PM UTC 24 156943952 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.596726859 Oct 02 10:58:19 PM UTC 24 Oct 02 10:58:47 PM UTC 24 20176744139 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.4288722230 Oct 02 10:58:45 PM UTC 24 Oct 02 10:58:48 PM UTC 24 229176311 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.562218590 Oct 02 10:58:46 PM UTC 24 Oct 02 10:58:48 PM UTC 24 169922520 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.1520098477 Oct 02 10:58:46 PM UTC 24 Oct 02 10:58:49 PM UTC 24 238569493 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.581898987 Oct 02 10:58:47 PM UTC 24 Oct 02 10:58:49 PM UTC 24 189695566 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.3320709976 Oct 02 10:58:46 PM UTC 24 Oct 02 10:58:49 PM UTC 24 235769538 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.774223608 Oct 02 10:58:48 PM UTC 24 Oct 02 10:58:50 PM UTC 24 150166798 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.470259116 Oct 02 10:58:08 PM UTC 24 Oct 02 10:58:51 PM UTC 24 5513128619 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.2510183664 Oct 02 10:57:58 PM UTC 24 Oct 02 10:58:52 PM UTC 24 28654534531 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.1763221134 Oct 02 10:58:49 PM UTC 24 Oct 02 10:58:52 PM UTC 24 279542473 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.2536773271 Oct 02 10:58:49 PM UTC 24 Oct 02 10:58:52 PM UTC 24 251155147 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.2574663572 Oct 02 10:58:49 PM UTC 24 Oct 02 10:58:52 PM UTC 24 459035733 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.1191565497 Oct 02 10:58:38 PM UTC 24 Oct 02 10:58:52 PM UTC 24 9213134693 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.210731243 Oct 02 10:58:50 PM UTC 24 Oct 02 10:58:52 PM UTC 24 151186541 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.552515850 Oct 02 10:58:50 PM UTC 24 Oct 02 10:58:53 PM UTC 24 184280176 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.3379512306 Oct 02 10:58:50 PM UTC 24 Oct 02 10:58:53 PM UTC 24 362186581 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2713400125 Oct 02 10:58:02 PM UTC 24 Oct 02 10:58:53 PM UTC 24 5115876705 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.2531039562 Oct 02 10:58:38 PM UTC 24 Oct 02 10:58:54 PM UTC 24 7370264837 ps
T525 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.3439434020 Oct 02 10:58:52 PM UTC 24 Oct 02 10:58:54 PM UTC 24 180956677 ps
T541 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.2104143040 Oct 02 10:58:51 PM UTC 24 Oct 02 10:58:54 PM UTC 24 225039028 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.3488152518 Oct 02 10:59:09 PM UTC 24 Oct 02 10:59:12 PM UTC 24 179693885 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.501918739 Oct 02 10:58:53 PM UTC 24 Oct 02 10:58:55 PM UTC 24 187186165 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.2172190492 Oct 02 10:58:54 PM UTC 24 Oct 02 10:58:56 PM UTC 24 53397985 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.2357657759 Oct 02 10:59:09 PM UTC 24 Oct 02 10:59:12 PM UTC 24 141626541 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.4201033039 Oct 02 10:59:11 PM UTC 24 Oct 02 10:59:14 PM UTC 24 181158492 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.758036596 Oct 02 10:58:54 PM UTC 24 Oct 02 10:58:57 PM UTC 24 363697394 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.641381797 Oct 02 10:58:30 PM UTC 24 Oct 02 10:58:57 PM UTC 24 3811165946 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.2982731357 Oct 02 10:58:53 PM UTC 24 Oct 02 10:58:57 PM UTC 24 572169369 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.3823384556 Oct 02 10:58:53 PM UTC 24 Oct 02 10:58:57 PM UTC 24 802874397 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.2003470719 Oct 02 10:58:26 PM UTC 24 Oct 02 10:58:57 PM UTC 24 19878358472 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.1431546571 Oct 02 10:58:55 PM UTC 24 Oct 02 10:58:58 PM UTC 24 141083833 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.1764201615 Oct 02 10:58:56 PM UTC 24 Oct 02 10:58:58 PM UTC 24 142952994 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.1467641239 Oct 02 10:58:55 PM UTC 24 Oct 02 10:58:58 PM UTC 24 159626921 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.1059261942 Oct 02 10:58:57 PM UTC 24 Oct 02 10:58:59 PM UTC 24 151511247 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.1928223174 Oct 02 10:58:57 PM UTC 24 Oct 02 10:58:59 PM UTC 24 205050408 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.879286957 Oct 02 10:58:57 PM UTC 24 Oct 02 10:59:00 PM UTC 24 257734700 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_enable.1322980977 Oct 02 10:58:58 PM UTC 24 Oct 02 10:59:00 PM UTC 24 54966085 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3460870435 Oct 02 10:58:40 PM UTC 24 Oct 02 10:59:01 PM UTC 24 2078851361 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.2377834103 Oct 02 10:58:09 PM UTC 24 Oct 02 10:59:01 PM UTC 24 29983876942 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.2624253728 Oct 02 10:58:57 PM UTC 24 Oct 02 10:59:01 PM UTC 24 537597716 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.3561572650 Oct 02 10:58:58 PM UTC 24 Oct 02 10:59:01 PM UTC 24 185178391 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.2373874222 Oct 02 10:58:59 PM UTC 24 Oct 02 10:59:01 PM UTC 24 201391948 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.3616816081 Oct 02 10:58:59 PM UTC 24 Oct 02 10:59:01 PM UTC 24 423490084 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.358752113 Oct 02 10:58:58 PM UTC 24 Oct 02 10:59:02 PM UTC 24 567937324 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.2718207713 Oct 02 10:58:54 PM UTC 24 Oct 02 10:59:02 PM UTC 24 4173339695 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.4220929075 Oct 02 10:58:59 PM UTC 24 Oct 02 10:59:02 PM UTC 24 290983855 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.1810970179 Oct 02 10:58:58 PM UTC 24 Oct 02 10:59:04 PM UTC 24 939938201 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.1239467909 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:05 PM UTC 24 171486107 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.3394689069 Oct 02 10:58:39 PM UTC 24 Oct 02 10:59:05 PM UTC 24 2411996222 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.3889820865 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:05 PM UTC 24 199728919 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.3312057695 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:05 PM UTC 24 227919303 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.4135801657 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:05 PM UTC 24 244648911 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.3847419191 Oct 02 10:58:01 PM UTC 24 Oct 02 10:59:07 PM UTC 24 33001802808 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.33336586 Oct 02 10:59:06 PM UTC 24 Oct 02 10:59:09 PM UTC 24 197922169 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.308003220 Oct 02 10:59:06 PM UTC 24 Oct 02 10:59:09 PM UTC 24 174679209 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.2091854719 Oct 02 10:59:06 PM UTC 24 Oct 02 10:59:09 PM UTC 24 242396763 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.1983167408 Oct 02 10:58:39 PM UTC 24 Oct 02 10:59:11 PM UTC 24 4156856462 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.709704186 Oct 02 10:59:11 PM UTC 24 Oct 02 10:59:14 PM UTC 24 149055964 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.2680141861 Oct 02 10:59:11 PM UTC 24 Oct 02 10:59:14 PM UTC 24 155278067 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.2038200596 Oct 02 10:58:30 PM UTC 24 Oct 02 10:59:14 PM UTC 24 4727405601 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.2727905154 Oct 02 10:58:27 PM UTC 24 Oct 02 10:59:15 PM UTC 24 28343820389 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.591126028 Oct 02 10:59:13 PM UTC 24 Oct 02 10:59:15 PM UTC 24 170809397 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.3027798624 Oct 02 10:59:12 PM UTC 24 Oct 02 10:59:15 PM UTC 24 177109112 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.1667058439 Oct 02 10:59:12 PM UTC 24 Oct 02 10:59:15 PM UTC 24 198910569 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.1311708128 Oct 02 10:59:15 PM UTC 24 Oct 02 10:59:17 PM UTC 24 37765399 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.1776871644 Oct 02 10:59:15 PM UTC 24 Oct 02 10:59:17 PM UTC 24 159827480 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.2361016557 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:17 PM UTC 24 9327576303 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.2495965094 Oct 02 10:58:48 PM UTC 24 Oct 02 10:59:17 PM UTC 24 20165009364 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.2750095736 Oct 02 10:59:17 PM UTC 24 Oct 02 10:59:19 PM UTC 24 183404037 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.1431882283 Oct 02 10:59:17 PM UTC 24 Oct 02 10:59:20 PM UTC 24 184010499 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.3925021242 Oct 02 10:59:17 PM UTC 24 Oct 02 10:59:20 PM UTC 24 212194107 ps
T614 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.1736192687 Oct 02 10:59:06 PM UTC 24 Oct 02 10:59:20 PM UTC 24 1751109876 ps
T615 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.539195192 Oct 02 10:59:17 PM UTC 24 Oct 02 10:59:20 PM UTC 24 222256150 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.456481886 Oct 02 10:58:48 PM UTC 24 Oct 02 10:59:21 PM UTC 24 6024312137 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.3107770205 Oct 02 10:58:17 PM UTC 24 Oct 02 10:59:21 PM UTC 24 22548027030 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.1286552101 Oct 02 10:59:05 PM UTC 24 Oct 02 10:59:22 PM UTC 24 1648560505 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.4084399514 Oct 02 10:59:19 PM UTC 24 Oct 02 10:59:22 PM UTC 24 135055156 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.4222757516 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:23 PM UTC 24 10298748634 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.3587239494 Oct 02 10:59:21 PM UTC 24 Oct 02 10:59:24 PM UTC 24 252882832 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.3114482113 Oct 02 10:59:22 PM UTC 24 Oct 02 10:59:24 PM UTC 24 209259459 ps
T617 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.4166302310 Oct 02 10:59:22 PM UTC 24 Oct 02 10:59:24 PM UTC 24 150577548 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.611301027 Oct 02 10:59:22 PM UTC 24 Oct 02 10:59:25 PM UTC 24 207360600 ps
T618 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.4170279171 Oct 02 10:58:51 PM UTC 24 Oct 02 10:59:25 PM UTC 24 3237139851 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.4259136844 Oct 02 10:58:54 PM UTC 24 Oct 02 10:59:25 PM UTC 24 20660032299 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.4265858140 Oct 02 10:59:22 PM UTC 24 Oct 02 10:59:26 PM UTC 24 467255981 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.2303948858 Oct 02 10:59:24 PM UTC 24 Oct 02 10:59:26 PM UTC 24 189595692 ps
T526 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.327276801 Oct 02 10:59:24 PM UTC 24 Oct 02 10:59:26 PM UTC 24 161860319 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.4150486636 Oct 02 10:59:24 PM UTC 24 Oct 02 10:59:26 PM UTC 24 164488967 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.639418545 Oct 02 10:59:24 PM UTC 24 Oct 02 10:59:26 PM UTC 24 217837260 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.2034322705 Oct 02 10:59:26 PM UTC 24 Oct 02 10:59:29 PM UTC 24 472341826 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.2567770564 Oct 02 10:59:27 PM UTC 24 Oct 02 10:59:29 PM UTC 24 49407389 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.3130300398 Oct 02 10:58:55 PM UTC 24 Oct 02 10:59:30 PM UTC 24 25362008758 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.9593553 Oct 02 10:59:26 PM UTC 24 Oct 02 10:59:30 PM UTC 24 852566136 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.2739380273 Oct 02 10:59:28 PM UTC 24 Oct 02 10:59:30 PM UTC 24 150904825 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.1395017353 Oct 02 10:59:27 PM UTC 24 Oct 02 10:59:31 PM UTC 24 556082758 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.487594925 Oct 02 10:59:29 PM UTC 24 Oct 02 10:59:31 PM UTC 24 143174229 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.3760903834 Oct 02 10:59:29 PM UTC 24 Oct 02 10:59:32 PM UTC 24 185718245 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.267428929 Oct 02 10:59:30 PM UTC 24 Oct 02 10:59:32 PM UTC 24 142829523 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.688248312 Oct 02 10:59:30 PM UTC 24 Oct 02 10:59:32 PM UTC 24 304115250 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.4023059531 Oct 02 10:58:58 PM UTC 24 Oct 02 10:59:32 PM UTC 24 4999273735 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.2692281573 Oct 02 10:59:04 PM UTC 24 Oct 02 10:59:33 PM UTC 24 3039140884 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.124222567 Oct 02 10:59:31 PM UTC 24 Oct 02 10:59:34 PM UTC 24 328156282 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.2676601389 Oct 02 10:59:32 PM UTC 24 Oct 02 10:59:34 PM UTC 24 159621786 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_enable.3608573955 Oct 02 10:59:33 PM UTC 24 Oct 02 10:59:35 PM UTC 24 56941123 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.2161829646 Oct 02 10:59:32 PM UTC 24 Oct 02 10:59:35 PM UTC 24 662231589 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.781563017 Oct 02 10:59:34 PM UTC 24 Oct 02 10:59:37 PM UTC 24 283938969 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.1197550376 Oct 02 11:00:00 PM UTC 24 Oct 02 11:00:02 PM UTC 24 166972862 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.3702986206 Oct 02 10:58:53 PM UTC 24 Oct 02 10:59:37 PM UTC 24 7779048970 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.1715192435 Oct 02 10:59:34 PM UTC 24 Oct 02 10:59:37 PM UTC 24 721071268 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.2004720025 Oct 02 10:59:06 PM UTC 24 Oct 02 10:59:37 PM UTC 24 2967915470 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.1039439102 Oct 02 10:58:40 PM UTC 24 Oct 02 10:59:38 PM UTC 24 1963376540 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.3028901202 Oct 02 10:59:34 PM UTC 24 Oct 02 10:59:38 PM UTC 24 1088389944 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.832130815 Oct 02 10:59:35 PM UTC 24 Oct 02 10:59:38 PM UTC 24 407864841 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.3677719081 Oct 02 10:59:39 PM UTC 24 Oct 02 10:59:41 PM UTC 24 141185654 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.3452480313 Oct 02 10:59:39 PM UTC 24 Oct 02 10:59:41 PM UTC 24 181516829 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.2902889610 Oct 02 10:59:39 PM UTC 24 Oct 02 10:59:42 PM UTC 24 254419149 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.2234486962 Oct 02 10:59:41 PM UTC 24 Oct 02 10:59:44 PM UTC 24 231713268 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.1601288510 Oct 02 10:59:28 PM UTC 24 Oct 02 10:59:45 PM UTC 24 9155442553 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.481754109 Oct 02 10:59:31 PM UTC 24 Oct 02 10:59:46 PM UTC 24 609955339 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.2593185742 Oct 02 10:58:46 PM UTC 24 Oct 02 10:59:47 PM UTC 24 19930895774 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.3412657459 Oct 02 10:59:19 PM UTC 24 Oct 02 10:59:49 PM UTC 24 20188073838 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3945394906 Oct 02 10:59:46 PM UTC 24 Oct 02 10:59:49 PM UTC 24 240016954 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.4016943049 Oct 02 10:58:24 PM UTC 24 Oct 02 10:59:51 PM UTC 24 6715026824 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.2794314436 Oct 02 10:59:49 PM UTC 24 Oct 02 10:59:52 PM UTC 24 184147490 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.1265179426 Oct 02 10:59:26 PM UTC 24 Oct 02 10:59:52 PM UTC 24 2479603324 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.1904770549 Oct 02 10:59:43 PM UTC 24 Oct 02 10:59:53 PM UTC 24 5010003441 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2752563729 Oct 02 10:58:30 PM UTC 24 Oct 02 10:59:53 PM UTC 24 44062783129 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.1093189048 Oct 02 10:59:53 PM UTC 24 Oct 02 10:59:55 PM UTC 24 185926299 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.2225131679 Oct 02 10:59:53 PM UTC 24 Oct 02 10:59:55 PM UTC 24 150766692 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.3561824244 Oct 02 10:59:32 PM UTC 24 Oct 02 10:59:56 PM UTC 24 2461857241 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.776032292 Oct 02 10:59:54 PM UTC 24 Oct 02 10:59:57 PM UTC 24 217175861 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.1171802955 Oct 02 10:59:54 PM UTC 24 Oct 02 10:59:57 PM UTC 24 207708663 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.3869311669 Oct 02 10:59:02 PM UTC 24 Oct 02 10:59:57 PM UTC 24 5225898498 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.3987539640 Oct 02 10:59:56 PM UTC 24 Oct 02 10:59:58 PM UTC 24 145169461 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.117463199 Oct 02 10:59:56 PM UTC 24 Oct 02 10:59:58 PM UTC 24 185290461 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.3776765969 Oct 02 10:58:48 PM UTC 24 Oct 02 10:59:58 PM UTC 24 11203542234 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.2068756330 Oct 02 10:58:53 PM UTC 24 Oct 02 10:59:58 PM UTC 24 2105873945 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.2722386443 Oct 02 10:59:15 PM UTC 24 Oct 02 10:59:59 PM UTC 24 14624345312 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.1379953264 Oct 02 10:59:57 PM UTC 24 Oct 02 10:59:59 PM UTC 24 145919944 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.2632237152 Oct 02 10:59:58 PM UTC 24 Oct 02 11:00:00 PM UTC 24 155609530 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.2362812244 Oct 02 10:59:58 PM UTC 24 Oct 02 11:00:00 PM UTC 24 241265175 ps
T652 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.3016380685 Oct 02 10:59:58 PM UTC 24 Oct 02 11:00:00 PM UTC 24 216651009 ps
T653 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.1763299971 Oct 02 10:58:09 PM UTC 24 Oct 02 11:00:01 PM UTC 24 3931708579 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.3370719396 Oct 02 11:00:00 PM UTC 24 Oct 02 11:00:02 PM UTC 24 53622393 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_max_inter_pkt_delay.4143561754 Oct 02 10:59:45 PM UTC 24 Oct 02 11:00:04 PM UTC 24 2348807388 ps
T655 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.3762360815 Oct 02 10:59:28 PM UTC 24 Oct 02 11:00:06 PM UTC 24 21331159110 ps
T656 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_out_transaction.4170744202 Oct 02 11:00:00 PM UTC 24 Oct 02 11:00:06 PM UTC 24 174214157 ps
T657 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_in_transaction.2322154539 Oct 02 11:00:00 PM UTC 24 Oct 02 11:00:06 PM UTC 24 203264542 ps
T658 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.1761234974 Oct 02 11:00:00 PM UTC 24 Oct 02 11:00:06 PM UTC 24 249136797 ps
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