Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1226	1			T88	1		T17	1		T104	3
range_16_to_126	151127	1			T1	1		T28	1		T29	12
fifteen	1514	1			T55	9		T170	75		T104	4
range_2_to_14	20599	1			T87	1		T88	2		T90	3
seven	1875	1			T88	1		T90	3		T72	2
one	1495	1			T169	1		T104	3		T414	1
zero	919	1			T2	1		T283	5		T541	3

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

11417

1

T30

1

T31

1

T32

2

three

14896

1

T30

1

T32

2

T87

18

---

Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	86	1			T119	1		T120	1		T457	1
range_127	three	61	1			T395	1		T445	1		T542	1
range_16_to_126	seven	9539	1			T30	1		T31	1		T32	2
range_16_to_126	three	13363	1			T30	1		T32	2		T87	17
fifteen	seven	156	1			T395	1		T473	1		T543	1
fifteen	three	54	1			T473	1		T543	1		T544	1
range_2_to_14	seven	1546	1			T169	1		T118	1		T104	4
range_2_to_14	three	1315	1			T87	1		T77	1		T104	6
seven	seven	218	1			T545	3		T396	1		T546	1
seven	three	110	1			T104	2		T547	3		T444	1
one	seven	35	1			T120	1		T444	1		T548	1
one	three	26	1			T169	1		T119	1		T181	1
zero	seven	55	1			T120	1		T549	13		T550	13
zero	three	77	1			T541	3		T119	1		T549	13