Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::crc5_cg

Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_crc5	3	0	3	100.00	100	1	1	0
cp_dir	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_crc5_X_dir	6	0	6	100.00	100	1	1	0

Summary for Variable cp_crc5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_crc5

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	4843	1			T32	2		T88	1		T33	1
leading_zero	4335	1			T87	2		T88	2		T163	2
trailing_zero	5174	1			T30	5		T87	1		T88	1

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Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109888

1

T1

1

T2

1

T28

1

auto[1]

66992

1

T29

5

T30

12

T32

12

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Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for cr_crc5_X_dir

Bins

cp_crc5	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	auto[0]	2831	1			T32	1		T557	1		T239	1
all_ones	auto[1]	2012	1			T32	1		T88	1		T33	1
leading_zero	auto[0]	2527	1			T87	1		T88	2		T163	1
leading_zero	auto[1]	1808	1			T87	1		T163	1		T50	1
trailing_zero	auto[0]	3464	1			T30	2		T88	1		T229	1
trailing_zero	auto[1]	1710	1			T30	3		T87	1		T165	6