Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109767

1

T1

1

T2

1

T28

1

auto[1]

45836

1

T29

5

T30

12

T32

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29107	1			T34	1		T38	1		T89	1
max_len_m1	825	1			T17	1		T50	1		T49	2
max_len_m2	822	1			T51	1		T86	1		T113	2
max_len_m3	814	1			T32	4		T24	1		T49	6
five	1169	1			T49	3		T56	1		T159	2
four	1189	1			T29	1		T32	2		T49	2
three	743	1			T49	1		T258	1		T558	1
one	861	1			T30	1		T49	2		T169	1
zero	11842	1			T2	1		T29	5		T30	5

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23527	1			T34	1		T38	1		T89	1
max_len	auto[1]	5580	1			T39	1		T5	1		T107	2
max_len_m1	auto[0]	574	1			T17	1		T50	1		T49	2
max_len_m1	auto[1]	251	1			T5	2		T108	1		T161	1
max_len_m2	auto[0]	553	1			T86	1		T113	2		T5	1
max_len_m2	auto[1]	269	1			T51	1		T5	1		T6	1
max_len_m3	auto[0]	564	1			T32	2		T24	1		T49	6
max_len_m3	auto[1]	250	1			T32	2		T161	1		T169	1
five	auto[0]	602	1			T49	3		T56	1		T159	1
five	auto[1]	567	1			T159	1		T107	1		T160	1
four	auto[0]	612	1			T29	1		T32	1		T49	2
four	auto[1]	577	1			T32	1		T68	1		T170	1
three	auto[0]	383	1			T49	1		T258	1		T558	1
three	auto[1]	360	1			T262	11		T559	1		T560	1
one	auto[0]	371	1			T30	1		T49	2		T169	1
one	auto[1]	490	1			T262	11		T561	1		T263	13
zero	auto[0]	543	1			T2	1		T37	1		T557	1
zero	auto[1]	11299	1			T29	5		T30	5		T37	1