Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137071

1

T1

2

T28

2

T29

14

auto[1]

77898

1

T29

10

T30

19

T32

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	16830	1			T32	4		T381	2		T53	2
endpoints[0x1]	20123	1			T32	4		T53	16		T159	4
endpoints[0x2]	20274	1			T30	5		T32	4		T89	2
endpoints[0x3]	21561	1			T30	2		T32	4		T36	4
endpoints[0x4]	16006	1			T29	24		T30	1		T32	4
endpoints[0x5]	13557	1			T30	5		T32	4		T37	4
endpoints[0x6]	14704	1			T30	5		T32	4		T557	2
endpoints[0x7]	13894	1			T30	2		T31	2		T32	4
endpoints[0x8]	18879	1			T28	2		T30	6		T32	4
endpoints[0x9]	24915	1			T30	4		T32	4		T62	4
endpoints[0xa]	15939	1			T30	10		T32	4		T17	1
endpoints[0xb]	18287	1			T1	2		T30	3		T32	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1434	1			T30	4		T34	2		T38	2
ack	103863	1			T1	1		T28	1		T29	12
data1	50509	1			T29	2		T30	10		T34	5
data0	59094	1			T1	1		T28	1		T29	10

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	107	1			T473	19		T458	15		T542	13
nak	auto[0]	endpoints[0x1]	106	1			T53	1		T260	1		T55	1
nak	auto[0]	endpoints[0x2]	109	1			T104	5		T119	14		T562	1
nak	auto[0]	endpoints[0x3]	102	1			T38	2		T119	10		T473	15
nak	auto[0]	endpoints[0x4]	95	1			T395	12		T563	1		T473	14
nak	auto[0]	endpoints[0x5]	83	1			T20	1		T140	1		T141	1
nak	auto[0]	endpoints[0x6]	115	1			T300	1		T119	14		T143	1
nak	auto[0]	endpoints[0x7]	128	1			T19	1		T104	7		T558	1
nak	auto[0]	endpoints[0x8]	93	1			T34	2		T120	14		T148	1
nak	auto[0]	endpoints[0x9]	102	1			T119	24		T151	1		T395	9
nak	auto[0]	endpoints[0xa]	112	1			T22	2		T104	12		T564	1
nak	auto[0]	endpoints[0xb]	104	1			T104	9		T120	13		T565	1
nak	auto[1]	endpoints[0x0]	10	1			T117	1		T566	1		T567	2
nak	auto[1]	endpoints[0x1]	12	1			T112	1		T568	1		T569	2
nak	auto[1]	endpoints[0x2]	19	1			T547	3		T570	1		T571	1
nak	auto[1]	endpoints[0x3]	15	1			T112	1		T117	1		T547	1
nak	auto[1]	endpoints[0x4]	11	1			T117	2		T545	1		T570	1
nak	auto[1]	endpoints[0x5]	20	1			T545	1		T547	1		T570	1
nak	auto[1]	endpoints[0x6]	15	1			T30	1		T547	1		T570	1
nak	auto[1]	endpoints[0x7]	14	1			T545	1		T570	3		T572	1
nak	auto[1]	endpoints[0x8]	15	1			T30	1		T547	1		T570	1
nak	auto[1]	endpoints[0x9]	11	1			T570	1		T573	1		T574	1
nak	auto[1]	endpoints[0xa]	14	1			T30	2		T112	1		T547	1
nak	auto[1]	endpoints[0xb]	22	1			T112	2		T545	1		T575	1
ack	auto[0]	endpoints[0x0]	4685	1			T32	1		T381	1		T53	1
ack	auto[0]	endpoints[0x1]	6443	1			T32	1		T53	7		T159	1
ack	auto[0]	endpoints[0x2]	6473	1			T30	1		T32	1		T89	1
ack	auto[0]	endpoints[0x3]	7189	1			T32	1		T36	1		T38	8
ack	auto[0]	endpoints[0x4]	4471	1			T29	7		T32	1		T163	1
ack	auto[0]	endpoints[0x5]	3434	1			T30	2		T32	1		T37	1
ack	auto[0]	endpoints[0x6]	3751	1			T30	1		T32	1		T557	1
ack	auto[0]	endpoints[0x7]	3578	1			T30	1		T31	1		T32	1
ack	auto[0]	endpoints[0x8]	6146	1			T28	1		T30	2		T32	1
ack	auto[0]	endpoints[0x9]	8841	1			T30	2		T32	1		T62	1
ack	auto[0]	endpoints[0xa]	4836	1			T30	2		T32	1		T22	8
ack	auto[0]	endpoints[0xb]	5686	1			T1	1		T30	1		T32	1
ack	auto[1]	endpoints[0x0]	3415	1			T32	1		T159	1		T112	1
ack	auto[1]	endpoints[0x1]	3320	1			T32	1		T159	1		T161	5
ack	auto[1]	endpoints[0x2]	3404	1			T30	1		T32	1		T110	2
ack	auto[1]	endpoints[0x3]	3280	1			T30	1		T32	1		T36	1
ack	auto[1]	endpoints[0x4]	3245	1			T29	5		T32	1		T163	1
ack	auto[1]	endpoints[0x5]	3022	1			T32	1		T39	1		T159	1
ack	auto[1]	endpoints[0x6]	3348	1			T32	1		T7	1		T159	1
ack	auto[1]	endpoints[0x7]	3064	1			T32	1		T159	1		T4	63
ack	auto[1]	endpoints[0x8]	3004	1			T32	1		T51	1		T159	1
ack	auto[1]	endpoints[0x9]	3278	1			T32	1		T62	1		T159	1
ack	auto[1]	endpoints[0xa]	2805	1			T30	1		T32	1		T164	1
ack	auto[1]	endpoints[0xb]	3145	1			T32	1		T40	4		T50	1
data1	auto[0]	endpoints[0x0]	2022	1			T160	3		T68	2		T165	2
data1	auto[0]	endpoints[0x1]	2946	1			T53	4		T112	2		T161	2
data1	auto[0]	endpoints[0x2]	2957	1			T30	1		T162	1		T167	1
data1	auto[0]	endpoints[0x3]	3286	1			T38	5		T167	2		T112	2
data1	auto[0]	endpoints[0x4]	1933	1			T29	2		T24	1		T90	1
data1	auto[0]	endpoints[0x5]	1438	1			T107	1		T161	1		T160	3
data1	auto[0]	endpoints[0x6]	1569	1			T169	2		T68	1		T165	2
data1	auto[0]	endpoints[0x7]	1536	1			T19	1		T56	3		T4	18
data1	auto[0]	endpoints[0x8]	2782	1			T30	1		T34	5		T51	1
data1	auto[0]	endpoints[0x9]	4153	1			T30	1		T107	1		T161	2
data1	auto[0]	endpoints[0xa]	2208	1			T22	5		T160	3		T576	1
data1	auto[0]	endpoints[0xb]	2602	1			T30	1		T50	1		T113	2
data1	auto[1]	endpoints[0x0]	1925	1			T112	1		T160	4		T68	2
data1	auto[1]	endpoints[0x1]	1822	1			T112	1		T161	3		T68	2
data1	auto[1]	endpoints[0x2]	1882	1			T110	1		T162	1		T167	1
data1	auto[1]	endpoints[0x3]	1819	1			T30	1		T167	2		T107	3
data1	auto[1]	endpoints[0x4]	1787	1			T30	1		T24	1		T90	1
data1	auto[1]	endpoints[0x5]	1664	1			T107	5		T161	3		T160	3
data1	auto[1]	endpoints[0x6]	1855	1			T169	2		T68	3		T165	2
data1	auto[1]	endpoints[0x7]	1647	1			T4	45		T161	2		T68	2
data1	auto[1]	endpoints[0x8]	1620	1			T30	1		T51	1		T107	5
data1	auto[1]	endpoints[0x9]	1828	1			T112	1		T107	5		T161	2
data1	auto[1]	endpoints[0xa]	1524	1			T30	2		T160	4		T111	5
data1	auto[1]	endpoints[0xb]	1704	1			T30	1		T40	2		T50	1
data0	auto[0]	endpoints[0x0]	3052	1			T32	1		T381	1		T53	1
data0	auto[0]	endpoints[0x1]	3913	1			T32	1		T53	4		T159	1
data0	auto[0]	endpoints[0x2]	3828	1			T32	1		T89	1		T18	1
data0	auto[0]	endpoints[0x3]	4353	1			T32	1		T36	1		T38	6
data0	auto[0]	endpoints[0x4]	2905	1			T29	5		T32	1		T163	1
data0	auto[0]	endpoints[0x5]	2433	1			T30	2		T32	1		T37	1
data0	auto[0]	endpoints[0x6]	2434	1			T30	1		T32	1		T557	1
data0	auto[0]	endpoints[0x7]	2438	1			T30	1		T31	1		T32	1
data0	auto[0]	endpoints[0x8]	3760	1			T28	1		T30	1		T32	1
data0	auto[0]	endpoints[0x9]	5142	1			T30	1		T32	1		T62	1
data0	auto[0]	endpoints[0xa]	3075	1			T30	2		T32	1		T17	1
data0	auto[0]	endpoints[0xb]	3498	1			T1	1		T32	1		T50	1
data0	auto[1]	endpoints[0x0]	1608	1			T32	1		T159	1		T112	1
data0	auto[1]	endpoints[0x1]	1558	1			T32	1		T159	1		T161	2
data0	auto[1]	endpoints[0x2]	1596	1			T30	2		T32	1		T110	3
data0	auto[1]	endpoints[0x3]	1512	1			T32	1		T36	1		T159	1
data0	auto[1]	endpoints[0x4]	1553	1			T29	5		T32	1		T163	1
data0	auto[1]	endpoints[0x5]	1460	1			T30	1		T32	1		T37	1
data0	auto[1]	endpoints[0x6]	1612	1			T30	2		T32	1		T7	1
data0	auto[1]	endpoints[0x7]	1482	1			T32	1		T159	1		T4	18
data0	auto[1]	endpoints[0x8]	1453	1			T32	1		T159	1		T107	1
data0	auto[1]	endpoints[0x9]	1552	1			T32	1		T62	1		T159	1
data0	auto[1]	endpoints[0xa]	1361	1			T30	1		T32	1		T164	1
data0	auto[1]	endpoints[0xb]	1516	1			T32	1		T40	5		T159	1