Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8142 1 T87 4 T88 2 T239 5
auto[1] 53725 1 T29 5 T30 12 T32 12


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54124 1 T29 5 T30 12 T32 12
auto[1] 7743 1 T88 1 T35 1 T107 21


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56240 1 T29 5 T30 12 T32 12
auto[1] 5627 1 T87 5 T88 3 T33 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4336 1 T87 3 T239 1 T229 2
pkt_types[PidTypeInToken] 57531 1 T29 5 T30 12 T32 12


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1409 1 T239 1 T169 1 T104 37
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 642 1 T87 2 T229 1 T104 14
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 103 1 T169 2 T118 1 T230 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 13 1 T454 2 T499 1 T434 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1317 1 T87 1 T229 1 T169 3
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 743 1 T227 1 T104 1 T119 31
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 93 1 T169 3 T230 1 T446 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 16 1 T397 1 T496 1 T511 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4023 1 T104 124 T384 1 T81 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 1850 1 T87 2 T88 1 T239 4
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 51 1 T88 1 T476 1 T496 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 51 1 T438 4 T454 1 T391 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41869 1 T29 5 T30 12 T32 12
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2271 1 T87 1 T88 2 T33 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7375 1 T35 1 T107 21 T108 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 41 1 T118 1 T577 1 T496 1

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