Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.46	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	1	53	98.15

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	1	53	98.15	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20270	1			T31	1		T56	1		T53	1
solo	73243	1			T2	1		T28	1		T29	7
empty	4824	1			T1	1		T87	1		T88	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20308	1			T4	63		T5	50		T6	32
solo	32432	1			T1	1		T87	15		T88	10
empty	45650	1			T2	1		T28	1		T29	7

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75202

1

T2

1

T28

1

T29

7

setup

23330

1

T1

1

T87

6

T88

6

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	36	1			T300	1		T301	1		T220	1
solo	145	1			T34	1		T38	1		T22	1
empty	82475	1			T1	1		T2	1		T28	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	1	53	98.15	1

Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[empty]	[empty]	[out]	0	1	1

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	3	1			T302	1		T303	1		T304	1
full	full	full	setup	1	1			T305	1		-	-		-	-
full	full	solo	out	2	1			T306	1		T307	1		-	-
full	full	solo	setup	6	1			T308	1		T309	1		T310	1
full	full	empty	out	15823	1			T4	24		T5	29		T6	14
full	full	empty	setup	4384	1			T4	39		T5	21		T6	18
full	solo	full	out	2	1			T311	1		T312	1		-	-
full	solo	full	setup	1	1			T313	1		-	-		-	-
full	solo	solo	out	4	1			T224	1		T314	1		T315	1
full	solo	solo	setup	4	1			T316	1		T317	1		T318	1
full	solo	empty	out	4	1			T319	1		T320	1		T321	1
full	solo	empty	setup	4	1			T322	1		T323	1		T324	1
full	empty	full	out	2	1			T325	1		T326	1		-	-
full	empty	full	setup	1	1			T327	1		-	-		-	-
full	empty	solo	out	4	1			T328	1		T329	1		T330	1
full	empty	solo	setup	13	1			T57	1		T331	1		T332	1
full	empty	empty	setup	10	1			T57	1		T331	1		T333	1
solo	full	full	out	1	1			T334	1		-	-		-	-
solo	full	full	setup	4	1			T335	1		T336	1		T337	1
solo	full	solo	out	3	1			T338	1		T339	1		T340	1
solo	full	solo	setup	1	1			T341	1		-	-		-	-
solo	full	empty	out	7	1			T53	1		T55	1		T342	1
solo	full	empty	setup	2	1			T343	1		T344	1		-	-
solo	solo	full	out	4	1			T301	1		T345	1		T346	1
solo	solo	full	setup	2	1			T222	1		T347	1		-	-
solo	solo	solo	out	6	1			T53	1		T55	1		T342	1
solo	solo	solo	setup	9	1			T53	1		T55	1		T342	1
solo	solo	empty	out	8229	1			T87	9		T88	4		T77	1
solo	solo	empty	setup	8215	1			T87	5		T88	5		T86	1
solo	empty	full	out	4	1			T348	1		T349	1		T350	1
solo	empty	full	setup	1	1			T351	1		-	-		-	-
solo	empty	solo	out	3	1			T352	1		T353	1		T354	1
solo	empty	solo	setup	56	1			T58	1		T300	1		T355	1
solo	empty	empty	out	5	1			T356	1		T357	1		T358	1
solo	empty	empty	setup	2106	1			T1	1		T87	1		T88	1
empty	full	full	out	2	1			T300	1		T225	1		-	-
empty	full	full	setup	1	1			T359	1		-	-		-	-
empty	full	solo	out	3	1			T226	1		T360	1		T361	1
empty	full	solo	setup	2	1			T221	1		T362	1		-	-
empty	full	empty	out	8	1			T31	1		T219	1		T363	1
empty	full	empty	setup	2	1			T364	1		T365	1		-	-
empty	solo	full	out	2	1			T366	1		T367	1		-	-
empty	solo	full	setup	2	1			T220	1		T368	1		-	-
empty	solo	solo	out	2	1			T369	1		T370	1		-	-
empty	solo	solo	setup	1	1			T371	1		-	-		-	-
empty	solo	empty	out	43233	1			T2	1		T28	1		T29	7
empty	solo	empty	setup	2	1			T372	1		T373	1		-	-
empty	empty	full	out	2	1			T374	1		T375	1		-	-
empty	empty	full	setup	1	1			T376	1		-	-		-	-
empty	empty	solo	out	1	1			T377	1		-	-		-	-
empty	empty	solo	setup	5	1			T378	1		T379	1		T380	1
empty	empty	empty	out	247	1			T34	1		T38	1		T22	1
empty	empty	empty	setup	154	1			T122	1		T167	1		T228	1