Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90870	1			T1	6		T2	3		T3	7
all_pins[1]	90870	1			T1	6		T2	3		T3	7
all_pins[2]	90870	1			T1	6		T2	3		T3	7
all_pins[3]	90870	1			T1	6		T2	3		T3	7
all_pins[4]	90870	1			T1	6		T2	3		T3	7
all_pins[5]	90870	1			T1	6		T2	3		T3	7
all_pins[6]	90870	1			T1	6		T2	3		T3	7
all_pins[7]	90870	1			T1	6		T2	3		T3	7
all_pins[8]	90870	1			T1	6		T2	3		T3	7
all_pins[9]	90870	1			T1	6		T2	3		T3	7
all_pins[10]	90870	1			T1	6		T2	3		T3	7
all_pins[11]	90870	1			T1	6		T2	3		T3	7
all_pins[12]	90870	1			T1	6		T2	3		T3	7
all_pins[13]	90870	1			T1	6		T2	3		T3	7
all_pins[14]	90870	1			T1	6		T2	3		T3	7
all_pins[15]	90870	1			T1	6		T2	3		T3	7
all_pins[16]	90870	1			T1	6		T2	3		T3	7
all_pins[17]	90870	1			T1	6		T2	3		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2905637	1			T1	191		T2	95		T3	222
values[0x1]	2203	1			T1	1		T2	1		T3	2
transitions[0x0=>0x1]	1982	1			T1	1		T2	1		T3	2
transitions[0x1=>0x0]	1982	1			T1	1		T2	1		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90764	1			T1	6		T2	3		T3	7
all_pins[0]	values[0x1]	106	1			T381	1		T382	1		T383	1
all_pins[0]	transitions[0x0=>0x1]	98	1			T381	1		T382	1		T383	1
all_pins[0]	transitions[0x1=>0x0]	865	1			T32	12		T36	1		T7	1
all_pins[1]	values[0x0]	89997	1			T1	6		T2	3		T3	7
all_pins[1]	values[0x1]	873	1			T32	12		T36	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	866	1			T32	12		T36	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	110	1			T41	1		T66	1		T67	1
all_pins[2]	values[0x0]	90753	1			T1	6		T2	3		T3	7
all_pins[2]	values[0x1]	117	1			T41	1		T66	1		T67	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T41	1		T66	1		T67	1
all_pins[2]	transitions[0x1=>0x0]	43	1			T49	1		T212	3		T289	2
all_pins[3]	values[0x0]	90810	1			T1	6		T2	3		T3	7
all_pins[3]	values[0x1]	60	1			T49	1		T211	1		T212	3
all_pins[3]	transitions[0x0=>0x1]	52	1			T49	1		T211	1		T212	3
all_pins[3]	transitions[0x1=>0x0]	50	1			T48	1		T210	1		T212	1
all_pins[4]	values[0x0]	90812	1			T1	6		T2	3		T3	7
all_pins[4]	values[0x1]	58	1			T48	1		T210	1		T212	1
all_pins[4]	transitions[0x0=>0x1]	44	1			T48	1		T210	1		T212	1
all_pins[4]	transitions[0x1=>0x0]	43	1			T211	3		T281	1		T289	1
all_pins[5]	values[0x0]	90813	1			T1	6		T2	3		T3	7
all_pins[5]	values[0x1]	57	1			T211	3		T281	1		T289	1
all_pins[5]	transitions[0x0=>0x1]	39	1			T211	1		T281	1		T289	1
all_pins[5]	transitions[0x1=>0x0]	110	1			T71	1		T72	1		T73	1
all_pins[6]	values[0x0]	90742	1			T1	6		T2	3		T3	7
all_pins[6]	values[0x1]	128	1			T71	1		T72	1		T73	1
all_pins[6]	transitions[0x0=>0x1]	120	1			T71	1		T72	1		T73	1
all_pins[6]	transitions[0x1=>0x0]	33	1			T52	1		T210	1		T211	1
all_pins[7]	values[0x0]	90829	1			T1	6		T2	3		T3	7
all_pins[7]	values[0x1]	41	1			T52	1		T210	1		T211	1
all_pins[7]	transitions[0x0=>0x1]	34	1			T52	1		T210	1		T211	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T54	1		T57	1		T59	1
all_pins[8]	values[0x0]	90799	1			T1	6		T2	3		T3	7
all_pins[8]	values[0x1]	71	1			T54	1		T57	1		T59	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T54	1		T57	1		T59	1
all_pins[8]	transitions[0x1=>0x0]	65	1			T3	2		T64	2		T65	2
all_pins[9]	values[0x0]	90799	1			T1	6		T2	3		T3	5
all_pins[9]	values[0x1]	71	1			T3	2		T64	2		T65	2
all_pins[9]	transitions[0x0=>0x1]	48	1			T3	2		T64	2		T65	2
all_pins[9]	transitions[0x1=>0x0]	64	1			T210	2		T211	1		T212	2
all_pins[10]	values[0x0]	90783	1			T1	6		T2	3		T3	7
all_pins[10]	values[0x1]	87	1			T210	3		T211	3		T212	2
all_pins[10]	transitions[0x0=>0x1]	72	1			T210	3		T211	3		T212	2
all_pins[10]	transitions[0x1=>0x0]	95	1			T74	1		T75	1		T76	1
all_pins[11]	values[0x0]	90760	1			T1	6		T2	3		T3	7
all_pins[11]	values[0x1]	110	1			T74	1		T75	1		T76	1
all_pins[11]	transitions[0x0=>0x1]	92	1			T74	1		T75	1		T76	1
all_pins[11]	transitions[0x1=>0x0]	41	1			T77	1		T78	1		T80	1
all_pins[12]	values[0x0]	90811	1			T1	6		T2	3		T3	7
all_pins[12]	values[0x1]	59	1			T77	1		T78	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	49	1			T77	1		T78	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	93	1			T2	1		T83	1		T84	1
all_pins[13]	values[0x0]	90767	1			T1	6		T2	2		T3	7
all_pins[13]	values[0x1]	103	1			T2	1		T83	1		T84	1
all_pins[13]	transitions[0x0=>0x1]	83	1			T2	1		T83	1		T84	1
all_pins[13]	transitions[0x1=>0x0]	45	1			T210	4		T211	1		T212	3
all_pins[14]	values[0x0]	90805	1			T1	6		T2	3		T3	7
all_pins[14]	values[0x1]	65	1			T210	4		T211	1		T212	3
all_pins[14]	transitions[0x0=>0x1]	52	1			T210	4		T212	1		T289	4
all_pins[14]	transitions[0x1=>0x0]	52	1			T210	2		T211	1		T212	2
all_pins[15]	values[0x0]	90805	1			T1	6		T2	3		T3	7
all_pins[15]	values[0x1]	65	1			T210	2		T211	2		T212	4
all_pins[15]	transitions[0x0=>0x1]	45	1			T210	1		T211	2		T212	2
all_pins[15]	transitions[0x1=>0x0]	51	1			T34	4		T38	4		T22	4
all_pins[16]	values[0x0]	90799	1			T1	6		T2	3		T3	7
all_pins[16]	values[0x1]	71	1			T34	4		T38	4		T22	4
all_pins[16]	transitions[0x0=>0x1]	62	1			T34	4		T38	4		T22	4
all_pins[16]	transitions[0x1=>0x0]	52	1			T1	1		T60	1		T61	1
all_pins[17]	values[0x0]	90809	1			T1	5		T2	3		T3	7
all_pins[17]	values[0x1]	61	1			T1	1		T60	1		T61	1
all_pins[17]	transitions[0x0=>0x1]	61	1			T1	1		T60	1		T61	1