Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4380	1			T88	2		T229	1		T161	10
invalid_ep[0xd]	4474	1			T229	2		T161	13		T104	80
invalid_ep[0xe]	4494	1			T88	3		T229	1		T161	10
invalid_ep[0xf]	4381	1			T88	1		T229	1		T161	3
endpoints[0x0]	12719	1			T2	1		T32	2		T88	1
endpoints[0x1]	13896	1			T32	2		T88	1		T53	8
endpoints[0x2]	14618	1			T30	3		T32	2		T88	1
endpoints[0x3]	14896	1			T30	1		T32	2		T87	18
endpoints[0x4]	12187	1			T29	12		T30	1		T32	2
endpoints[0x5]	10991	1			T30	3		T32	2		T88	4
endpoints[0x6]	11625	1			T30	3		T32	2		T87	2
endpoints[0x7]	11417	1			T30	1		T31	1		T32	2
endpoints[0x8]	13770	1			T28	1		T30	3		T32	2
endpoints[0x9]	16781	1			T30	2		T32	2		T88	1
endpoints[0xa]	12835	1			T30	5		T32	2		T87	6
endpoints[0xb]	13416	1			T1	1		T30	2		T32	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23330	1			T1	1		T87	6		T88	6
pkt_types[PidTypeOutToken]	75202	1			T2	1		T28	1		T29	7
pkt_types[PidTypeInToken]	61343	1			T29	5		T30	12		T32	12

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	929	1			T88	1		T229	1		T118	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	964	1			T104	21		T119	29		T120	27
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	946	1			T104	15		T119	25		T120	28
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	963	1			T88	1		T118	1		T104	19
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1677	1			T53	1		T239	2		T160	2
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1676	1			T229	1		T161	2		T165	5
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1721	1			T18	1		T162	1		T167	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1735	1			T87	4		T167	3		T161	2
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1675	1			T24	1		T90	1		T60	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1549	1			T88	2		T122	1		T229	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1624	1			T87	1		T121	1		T229	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1499	1			T88	1		T86	1		T4	39
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1554	1			T51	1		T239	1		T229	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1669	1			T88	1		T239	1		T229	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1568	1			T87	1		T160	3		T171	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1581	1			T1	1		T50	1		T229	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1512	1			T88	1		T161	10		T118	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1579	1			T229	1		T161	13		T104	25
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1553	1			T88	2		T161	10		T104	17
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1534	1			T161	3		T104	22		T81	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	4827	1			T2	1		T32	1		T381	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	6669	1			T32	1		T53	8		T159	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6678	1			T30	1		T32	1		T89	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	7416	1			T32	1		T87	6		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4730	1			T29	7		T32	1		T163	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	3692	1			T30	2		T32	1		T37	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	3864	1			T30	1		T32	1		T88	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4149	1			T30	1		T31	1		T32	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	6410	1			T28	1		T30	2		T32	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	9154	1			T30	2		T32	1		T62	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5396	1			T30	2		T32	1		T87	3
pkt_types[PidTypeOutToken]	endpoints[0xb]	6039	1			T30	1		T32	1		T50	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	958	1			T104	29		T414	1		T119	41
pkt_types[PidTypeInToken]	invalid_ep[0xd]	939	1			T229	1		T104	18		T119	30
pkt_types[PidTypeInToken]	invalid_ep[0xe]	996	1			T88	1		T104	17		T119	37
pkt_types[PidTypeInToken]	invalid_ep[0xf]	919	1			T104	12		T119	23		T120	25
pkt_types[PidTypeInToken]	endpoints[0x0]	5129	1			T32	1		T88	1		T159	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4432	1			T32	1		T159	1		T112	1
pkt_types[PidTypeInToken]	endpoints[0x2]	5131	1			T30	2		T32	1		T110	4
pkt_types[PidTypeInToken]	endpoints[0x3]	4641	1			T30	1		T32	1		T87	4
pkt_types[PidTypeInToken]	endpoints[0x4]	4637	1			T29	5		T30	1		T32	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4652	1			T30	1		T32	1		T88	1
pkt_types[PidTypeInToken]	endpoints[0x6]	5018	1			T30	2		T32	1		T87	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4689	1			T32	1		T35	1		T86	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4760	1			T30	1		T32	1		T51	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4897	1			T32	1		T62	1		T159	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4842	1			T30	3		T32	1		T87	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4703	1			T30	1		T32	1		T87	1