Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	256	1			T210	7		T211	7		T212	7
all_values[1]	256	1			T210	7		T211	7		T212	7
all_values[2]	256	1			T210	7		T211	7		T212	7
all_values[3]	256	1			T210	7		T211	7		T212	7
all_values[4]	256	1			T210	7		T211	7		T212	7
all_values[5]	256	1			T210	7		T211	7		T212	7
all_values[6]	256	1			T210	7		T211	7		T212	7
all_values[7]	256	1			T210	7		T211	7		T212	7
all_values[8]	256	1			T210	7		T211	7		T212	7
all_values[9]	256	1			T210	7		T211	7		T212	7
all_values[10]	256	1			T210	7		T211	7		T212	7
all_values[11]	256	1			T210	7		T211	7		T212	7
all_values[12]	256	1			T210	7		T211	7		T212	7
all_values[13]	256	1			T210	7		T211	7		T212	7
all_values[14]	256	1			T210	7		T211	7		T212	7
all_values[15]	256	1			T210	7		T211	7		T212	7
all_values[16]	256	1			T210	7		T211	7		T212	7
all_values[17]	256	1			T210	7		T211	7		T212	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6110

1

T210

167

T211

154

T212

165

auto[1]

2082

1

T210

57

T211

70

T212

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5631

1

T210

158

T211

151

T212

152

auto[1]

2561

1

T210

66

T211

73

T212

72

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4851

1

T210

142

T211

130

T212

131

auto[1]

3341

1

T210

82

T211

94

T212

93

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	83	1			T210	2		T211	1		T212	2
all_values[0]	auto[0]	auto[1]	auto[0]	71	1			T210	4		T211	3		T212	2
all_values[0]	auto[1]	auto[0]	auto[1]	59	1			T211	1		T212	1		T289	5
all_values[0]	auto[1]	auto[1]	auto[1]	43	1			T210	1		T211	2		T212	2
all_values[1]	auto[0]	auto[0]	auto[0]	87	1			T210	1		T211	2		T281	2
all_values[1]	auto[0]	auto[1]	auto[0]	72	1			T210	2		T211	3		T212	4
all_values[1]	auto[1]	auto[0]	auto[1]	58	1			T210	4		T212	3		T281	1
all_values[1]	auto[1]	auto[1]	auto[1]	39	1			T211	2		T290	2		T291	2
all_values[2]	auto[0]	auto[0]	auto[0]	35	1			T212	3		T281	2		T289	2
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T210	2		T211	3		T281	1
all_values[2]	auto[0]	auto[1]	auto[0]	38	1			T212	2		T290	2		T291	4
all_values[2]	auto[0]	auto[1]	auto[1]	32	1			T210	2		T289	1		T291	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T211	1		T281	1		T289	2
all_values[2]	auto[1]	auto[1]	auto[1]	42	1			T210	3		T211	3		T212	2
all_values[3]	auto[0]	auto[0]	auto[0]	53	1			T210	2		T281	2		T289	3
all_values[3]	auto[0]	auto[0]	auto[1]	28	1			T210	2		T290	1		T291	1
all_values[3]	auto[0]	auto[1]	auto[0]	43	1			T210	2		T211	4		T281	1
all_values[3]	auto[0]	auto[1]	auto[1]	26	1			T211	1		T212	3		T292	1
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T210	1		T212	3		T289	3
all_values[3]	auto[1]	auto[1]	auto[1]	42	1			T211	2		T212	1		T281	1
all_values[4]	auto[0]	auto[0]	auto[0]	67	1			T210	2		T211	3		T212	5
all_values[4]	auto[0]	auto[0]	auto[1]	19	1			T211	1		T292	1		T291	1
all_values[4]	auto[0]	auto[1]	auto[0]	52	1			T210	2		T211	1		T289	2
all_values[4]	auto[0]	auto[1]	auto[1]	27	1			T210	1		T289	1		T293	2
all_values[4]	auto[1]	auto[0]	auto[1]	49	1			T210	1		T211	2		T281	2
all_values[4]	auto[1]	auto[1]	auto[1]	42	1			T210	1		T212	2		T289	1
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T210	1		T212	2		T289	1
all_values[5]	auto[0]	auto[0]	auto[1]	38	1			T210	1		T211	2		T212	1
all_values[5]	auto[0]	auto[1]	auto[0]	37	1			T210	2		T281	1		T289	1
all_values[5]	auto[0]	auto[1]	auto[1]	21	1			T211	1		T293	1		T294	2
all_values[5]	auto[1]	auto[0]	auto[1]	60	1			T210	3		T211	2		T212	3
all_values[5]	auto[1]	auto[1]	auto[1]	54	1			T211	2		T212	1		T281	2
all_values[6]	auto[0]	auto[0]	auto[0]	52	1			T210	2		T290	1		T293	1
all_values[6]	auto[0]	auto[0]	auto[1]	17	1			T211	1		T212	2		T289	1
all_values[6]	auto[0]	auto[1]	auto[0]	43	1			T210	4		T211	1		T289	2
all_values[6]	auto[0]	auto[1]	auto[1]	34	1			T211	1		T212	1		T281	1
all_values[6]	auto[1]	auto[0]	auto[1]	57	1			T211	2		T212	1		T281	3
all_values[6]	auto[1]	auto[1]	auto[1]	53	1			T210	1		T211	2		T212	3
all_values[7]	auto[0]	auto[0]	auto[0]	81	1			T210	2		T211	2		T212	1
all_values[7]	auto[0]	auto[1]	auto[0]	72	1			T210	2		T211	1		T212	4
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T210	1		T211	1		T281	1
all_values[7]	auto[1]	auto[1]	auto[1]	34	1			T210	2		T211	3		T212	2
all_values[8]	auto[0]	auto[0]	auto[0]	84	1			T210	2		T212	3		T281	1
all_values[8]	auto[0]	auto[1]	auto[0]	66	1			T210	2		T211	5		T212	2
all_values[8]	auto[1]	auto[0]	auto[1]	73	1			T210	3		T212	2		T281	2
all_values[8]	auto[1]	auto[1]	auto[1]	33	1			T211	2		T289	2		T292	2
all_values[9]	auto[0]	auto[0]	auto[0]	54	1			T210	2		T212	1		T289	2
all_values[9]	auto[0]	auto[0]	auto[1]	18	1			T210	1		T295	1		T296	1
all_values[9]	auto[0]	auto[1]	auto[0]	57	1			T210	2		T211	1		T212	3
all_values[9]	auto[0]	auto[1]	auto[1]	24	1			T210	1		T211	1		T289	2
all_values[9]	auto[1]	auto[0]	auto[1]	57	1			T210	1		T211	2		T212	3
all_values[9]	auto[1]	auto[1]	auto[1]	46	1			T211	3		T289	1		T293	2
all_values[10]	auto[0]	auto[0]	auto[0]	57	1			T210	1		T211	1		T212	2
all_values[10]	auto[0]	auto[0]	auto[1]	21	1			T210	1		T293	2		T297	1
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T212	1		T281	1		T289	1
all_values[10]	auto[0]	auto[1]	auto[1]	40	1			T210	1		T211	2		T212	1
all_values[10]	auto[1]	auto[0]	auto[1]	49	1			T210	1		T211	2		T212	2
all_values[10]	auto[1]	auto[1]	auto[1]	57	1			T210	3		T211	2		T212	1
all_values[11]	auto[0]	auto[0]	auto[0]	63	1			T210	3		T211	1		T212	4
all_values[11]	auto[0]	auto[0]	auto[1]	21	1			T210	1		T212	1		T289	1
all_values[11]	auto[0]	auto[1]	auto[0]	49	1			T211	3		T212	1		T281	1
all_values[11]	auto[0]	auto[1]	auto[1]	30	1			T211	1		T281	1		T290	3
all_values[11]	auto[1]	auto[0]	auto[1]	55	1			T210	3		T211	1		T212	1
all_values[11]	auto[1]	auto[1]	auto[1]	38	1			T211	1		T281	1		T290	2
all_values[12]	auto[0]	auto[0]	auto[0]	63	1			T210	1		T211	4		T212	4
all_values[12]	auto[0]	auto[0]	auto[1]	21	1			T210	1		T211	1		T290	1
all_values[12]	auto[0]	auto[1]	auto[0]	46	1			T210	1		T211	1		T281	1
all_values[12]	auto[0]	auto[1]	auto[1]	21	1			T210	1		T212	1		T289	2
all_values[12]	auto[1]	auto[0]	auto[1]	55	1			T210	3		T211	1		T212	1
all_values[12]	auto[1]	auto[1]	auto[1]	50	1			T212	1		T289	3		T290	1
all_values[13]	auto[0]	auto[0]	auto[0]	57	1			T210	3		T211	3		T289	1
all_values[13]	auto[0]	auto[0]	auto[1]	27	1			T211	1		T281	1		T289	1
all_values[13]	auto[0]	auto[1]	auto[0]	47	1			T210	3		T211	1		T212	4
all_values[13]	auto[0]	auto[1]	auto[1]	23	1			T281	1		T290	1		T291	1
all_values[13]	auto[1]	auto[0]	auto[1]	58	1			T210	1		T211	1		T212	3
all_values[13]	auto[1]	auto[1]	auto[1]	44	1			T211	1		T289	1		T290	1
all_values[14]	auto[0]	auto[0]	auto[0]	52	1			T210	2		T211	3		T281	1
all_values[14]	auto[0]	auto[0]	auto[1]	25	1			T212	2		T289	1		T293	1
all_values[14]	auto[0]	auto[1]	auto[0]	44	1			T211	2		T281	2		T290	1
all_values[14]	auto[0]	auto[1]	auto[1]	29	1			T210	3		T211	1		T289	1
all_values[14]	auto[1]	auto[0]	auto[1]	58	1			T212	3		T281	1		T289	1
all_values[14]	auto[1]	auto[1]	auto[1]	48	1			T210	2		T211	1		T212	2
all_values[15]	auto[0]	auto[0]	auto[0]	62	1			T210	1		T281	1		T289	3
all_values[15]	auto[0]	auto[0]	auto[1]	26	1			T210	2		T212	2		T289	1
all_values[15]	auto[0]	auto[1]	auto[0]	46	1			T210	1		T211	1		T289	1
all_values[15]	auto[0]	auto[1]	auto[1]	27	1			T210	1		T211	1		T212	4
all_values[15]	auto[1]	auto[0]	auto[1]	47	1			T210	1		T211	2		T281	1
all_values[15]	auto[1]	auto[1]	auto[1]	48	1			T210	1		T211	3		T212	1
all_values[16]	auto[0]	auto[0]	auto[0]	60	1			T210	1		T211	3		T212	2
all_values[16]	auto[0]	auto[0]	auto[1]	22	1			T210	1		T298	1		T299	1
all_values[16]	auto[0]	auto[1]	auto[0]	38	1			T281	1		T289	3		T290	2
all_values[16]	auto[0]	auto[1]	auto[1]	20	1			T211	1		T212	1		T292	3
all_values[16]	auto[1]	auto[0]	auto[1]	75	1			T210	3		T211	2		T212	2
all_values[16]	auto[1]	auto[1]	auto[1]	41	1			T210	2		T211	1		T212	2
all_values[17]	auto[0]	auto[0]	auto[0]	72	1			T210	2		T211	1		T281	1
all_values[17]	auto[0]	auto[1]	auto[0]	66	1			T210	3		T211	2		T212	2
all_values[17]	auto[1]	auto[0]	auto[1]	63	1			T210	1		T211	3		T212	2
all_values[17]	auto[1]	auto[1]	auto[1]	55	1			T210	1		T211	1		T212	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal