Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	170424	1			T1	7		T2	4		T3	3
all_values[1]	170424	1			T1	7		T2	4		T3	3
all_values[2]	170424	1			T1	7		T2	4		T3	3
all_values[3]	170424	1			T1	7		T2	4		T3	3
all_values[4]	170424	1			T1	7		T2	4		T3	3
all_values[5]	170424	1			T1	7		T2	4		T3	3
all_values[6]	170424	1			T1	7		T2	4		T3	3
all_values[7]	170424	1			T1	7		T2	4		T3	3
all_values[8]	170424	1			T1	7		T2	4		T3	3
all_values[9]	170424	1			T1	7		T2	4		T3	3
all_values[10]	170424	1			T1	7		T2	4		T3	3
all_values[11]	170424	1			T1	7		T2	4		T3	3
all_values[12]	170424	1			T1	7		T2	4		T3	3
all_values[13]	170424	1			T1	7		T2	4		T3	3
all_values[14]	170424	1			T1	7		T2	4		T3	3
all_values[15]	170424	1			T1	7		T2	4		T3	3
all_values[16]	170424	1			T1	7		T2	4		T3	3
all_values[17]	170424	1			T1	7		T2	4		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5443863

1

T1

219

T2

128

T3

94

auto[1]

9705

1

T1

5

T3

2

T27

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4676517

1

T1

210

T2

110

T3

85

auto[1]

777051

1

T1

14

T2

18

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142250	1			T1	7		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	24861	1			T2	1		T27	3		T35	1
all_values[0]	auto[1]	auto[0]	3198	1			T33	3		T57	5		T49	3
all_values[0]	auto[1]	auto[1]	115	1			T33	1		T539	1		T540	1
all_values[1]	auto[0]	auto[0]	165983	1			T1	7		T2	4		T3	3
all_values[1]	auto[0]	auto[1]	3043	1			T29	2		T31	2		T37	3
all_values[1]	auto[1]	auto[0]	522	1			T30	2		T34	2		T36	2
all_values[1]	auto[1]	auto[1]	876	1			T30	12		T34	1		T36	12
all_values[2]	auto[0]	auto[0]	4376	1			T1	6		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	165797	1			T1	1		T2	3		T3	2
all_values[2]	auto[1]	auto[0]	135	1			T41	1		T56	1		T71	1
all_values[2]	auto[1]	auto[1]	116	1			T41	1		T56	1		T71	1
all_values[3]	auto[0]	auto[0]	168467	1			T1	7		T2	4		T3	3
all_values[3]	auto[0]	auto[1]	313	1			T21	1		T4	1		T6	1
all_values[3]	auto[1]	auto[0]	1587	1			T21	1484		T215	2		T212	4
all_values[3]	auto[1]	auto[1]	57	1			T21	1		T215	4		T212	1
all_values[4]	auto[0]	auto[0]	4347	1			T1	6		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	165920	1			T1	1		T2	3		T3	2
all_values[4]	auto[1]	auto[0]	86	1			T215	6		T212	1		T214	2
all_values[4]	auto[1]	auto[1]	71	1			T212	3		T214	2		T281	2
all_values[5]	auto[0]	auto[0]	169915	1			T1	7		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	365	1			T7	1		T8	1		T4	1
all_values[5]	auto[1]	auto[0]	79	1			T215	1		T214	3		T281	1
all_values[5]	auto[1]	auto[1]	65	1			T212	2		T214	3		T281	3
all_values[6]	auto[0]	auto[0]	170000	1			T1	7		T2	4		T3	3
all_values[6]	auto[0]	auto[1]	221	1			T8	1		T4	1		T72	1
all_values[6]	auto[1]	auto[0]	92	1			T212	1		T214	4		T281	7
all_values[6]	auto[1]	auto[1]	111	1			T73	1		T74	1		T75	1
all_values[7]	auto[0]	auto[0]	115286	1			T3	3		T41	2		T42	2
all_values[7]	auto[0]	auto[1]	54986	1			T1	7		T2	4		T27	6
all_values[7]	auto[1]	auto[0]	101	1			T58	2		T212	1		T214	5
all_values[7]	auto[1]	auto[1]	51	1			T58	1		T215	2		T212	2
all_values[8]	auto[0]	auto[0]	169533	1			T1	7		T2	4		T3	3
all_values[8]	auto[0]	auto[1]	196	1			T63	2		T222	2		T309	2
all_values[8]	auto[1]	auto[0]	611	1			T20	10		T61	10		T62	10
all_values[8]	auto[1]	auto[1]	84	1			T20	1		T64	1		T65	1
all_values[9]	auto[0]	auto[0]	170161	1			T1	2		T2	4		T3	3
all_values[9]	auto[0]	auto[1]	90	1			T215	1		T212	1		T214	5
all_values[9]	auto[1]	auto[0]	101	1			T1	3		T69	3		T70	3
all_values[9]	auto[1]	auto[1]	72	1			T1	2		T69	2		T70	2
all_values[10]	auto[0]	auto[0]	169878	1			T1	7		T2	4		T3	3
all_values[10]	auto[0]	auto[1]	379	1			T31	1		T32	1		T68	1
all_values[10]	auto[1]	auto[0]	108	1			T215	3		T212	2		T281	3
all_values[10]	auto[1]	auto[1]	59	1			T215	2		T214	3		T283	4
all_values[11]	auto[0]	auto[0]	169422	1			T1	7		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	736	1			T3	1		T22	4		T57	3
all_values[11]	auto[1]	auto[0]	151	1			T17	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	115	1			T17	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	170031	1			T1	7		T2	4		T3	3
all_values[12]	auto[0]	auto[1]	205	1			T82	1		T83	1		T84	1
all_values[12]	auto[1]	auto[0]	107	1			T79	2		T80	2		T81	2
all_values[12]	auto[1]	auto[1]	81	1			T79	1		T80	1		T81	1
all_values[13]	auto[0]	auto[0]	170049	1			T1	7		T2	4		T3	1
all_values[13]	auto[0]	auto[1]	72	1			T82	1		T83	1		T84	1
all_values[13]	auto[1]	auto[0]	176	1			T3	1		T85	1		T86	1
all_values[13]	auto[1]	auto[1]	127	1			T3	1		T85	1		T86	1
all_values[14]	auto[0]	auto[0]	35522	1			T1	7		T2	4		T3	3
all_values[14]	auto[0]	auto[1]	134743	1			T41	1		T7	2		T21	1486
all_values[14]	auto[1]	auto[0]	113	1			T215	2		T212	3		T214	3
all_values[14]	auto[1]	auto[1]	46	1			T214	1		T281	1		T282	4
all_values[15]	auto[0]	auto[0]	4395	1			T1	6		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	165867	1			T1	1		T2	3		T3	2
all_values[15]	auto[1]	auto[0]	100	1			T215	1		T214	1		T281	1
all_values[15]	auto[1]	auto[1]	62	1			T212	3		T214	2		T281	1
all_values[16]	auto[0]	auto[0]	169375	1			T1	7		T2	4		T3	3
all_values[16]	auto[0]	auto[1]	876	1			T31	1		T38	1		T17	1
all_values[16]	auto[1]	auto[0]	105	1			T22	4		T76	4		T215	1
all_values[16]	auto[1]	auto[1]	68	1			T22	4		T76	4		T215	2
all_values[17]	auto[0]	auto[0]	114115	1			T1	5		T27	1		T42	2
all_values[17]	auto[0]	auto[1]	56152	1			T1	2		T2	4		T3	3
all_values[17]	auto[1]	auto[0]	104	1			T27	2		T66	2		T67	2
all_values[17]	auto[1]	auto[1]	53	1			T27	1		T66	1		T67	1