Name |
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/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.925181376 |
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/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.974888783 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.1908963906 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.3497298625 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1864301255 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.2384781534 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1527814625 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1374189434 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1590424236 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.4031636757 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.801872701 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.69553778 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2952436138 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.2652591166 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2179270379 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.1134082118 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.277878410 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1275909598 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.1491806546 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2331390102 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.1365877308 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.3565960924 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2719510668 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.2722695409 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.394525492 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2574964992 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.1806402809 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.736610289 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2348213122 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1738001984 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3210523343 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.1246839731 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.261769016 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3030394776 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.2620784574 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.535084661 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3577757977 |
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/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.1258383068 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2602196362 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.3543511594 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.457136420 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2510875295 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.227850697 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1800333751 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.4077179300 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.2162183923 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2841806999 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4117054516 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.1727683553 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2881928888 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.2884672687 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.1194825844 |
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/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.822101264 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.60061801 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.12561797 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1907427265 |
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/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3469971586 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1651448841 |
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.705627488 |
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