Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1100	1			T124	123		T121	5		T548	2
range_16_to_126	162336	1			T2	1		T42	7		T29	19
fifteen	624	1			T27	1		T121	11		T549	1
range_2_to_14	14147	1			T28	1		T42	2		T43	4
seven	449	1			T6	1		T398	1		T121	6
one	1421	1			T380	1		T130	2		T118	1
zero	1749	1			T3	1		T43	1		T117	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

14907

1

T30

2

T31

2

T36

2

three

13788

1

T2

1

T28

1

T30

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	63	1			T550	42		T533	1		T551	1
range_127	three	82	1			T122	1		T437	1		T438	1
range_16_to_126	seven	13524	1			T30	2		T31	2		T36	2
range_16_to_126	three	12498	1			T2	1		T30	2		T31	3
fifteen	seven	153	1			T122	1		T123	1		T186	3
fifteen	three	47	1			T121	1		T122	1		T123	2
range_2_to_14	seven	1043	1			T6	1		T99	70		T118	1
range_2_to_14	three	990	1			T28	1		T99	57		T528	1
seven	seven	19	1			T122	1		T123	1		T552	1
seven	three	34	1			T170	2		T553	1		T436	1
one	seven	37	1			T121	2		T122	1		T382	1
one	three	60	1			T122	1		T186	1		T554	2
zero	seven	87	1			T121	2		T186	51		T459	2
zero	three	111	1			T122	1		T186	62		T555	27