Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113150

1

T2

1

T3

1

T27

1

auto[1]

45327

1

T28

1

T29

11

T30

12

---

Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28817	1			T18	1		T19	2		T21	3
max_len_m1	853	1			T30	2		T31	2		T21	3
max_len_m2	908	1			T31	1		T36	2		T21	2
max_len_m3	879	1			T21	4		T4	2		T57	1
five	1062	1			T21	2		T4	2		T68	1
four	1144	1			T36	2		T21	1		T22	2
three	804	1			T31	2		T36	2		T21	2
one	873	1			T21	1		T6	3		T109	2
zero	11481	1			T3	1		T28	1		T29	11

---

Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23492	1			T18	1		T19	1		T21	3
max_len	auto[1]	5325	1			T19	1		T6	1		T124	1
max_len_m1	auto[0]	585	1			T30	1		T31	1		T21	3
max_len_m1	auto[1]	268	1			T30	1		T31	1		T4	1
max_len_m2	auto[0]	618	1			T31	1		T36	1		T21	2
max_len_m2	auto[1]	290	1			T36	1		T68	1		T6	2
max_len_m3	auto[0]	604	1			T21	4		T4	1		T57	1
max_len_m3	auto[1]	275	1			T4	1		T6	1		T124	3
five	auto[0]	565	1			T21	2		T4	1		T68	1
five	auto[1]	497	1			T4	1		T5	1		T6	2
four	auto[0]	599	1			T36	1		T21	1		T22	2
four	auto[1]	545	1			T36	1		T6	1		T171	1
three	auto[0]	433	1			T31	1		T36	1		T21	2
three	auto[1]	371	1			T31	1		T36	1		T99	5
one	auto[0]	360	1			T21	1		T6	3		T109	1
one	auto[1]	513	1			T109	1		T99	5		T100	4
zero	auto[0]	547	1			T3	1		T30	1		T36	1
zero	auto[1]	10934	1			T28	1		T29	11		T30	1