Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137302

1

T2

2

T27

2

T29

16

auto[1]

77951

1

T28

2

T29

22

T30

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	22494	1			T30	4		T31	7		T36	4
endpoints[0x1]	19507	1			T30	4		T31	8		T36	4
endpoints[0x2]	15147	1			T30	4		T31	9		T36	4
endpoints[0x3]	17899	1			T2	2		T28	2		T30	4
endpoints[0x4]	16615	1			T30	4		T31	8		T34	4
endpoints[0x5]	19207	1			T29	38		T30	4		T31	6
endpoints[0x6]	13215	1			T27	2		T30	4		T31	4
endpoints[0x7]	21063	1			T30	4		T31	4		T36	4
endpoints[0x8]	13314	1			T30	4		T31	3		T35	2
endpoints[0x9]	19342	1			T30	4		T31	6		T32	5
endpoints[0xa]	17586	1			T30	4		T36	4		T4	28
endpoints[0xb]	19864	1			T30	4		T31	11		T36	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1327	1			T31	5		T22	2		T76	2
ack	104239	1			T2	1		T27	1		T28	1
data1	50629	1			T29	6		T31	15		T32	2
data0	58984	1			T2	1		T27	1		T28	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	68	1			T559	1		T133	1		T531	13
nak	auto[0]	endpoints[0x1]	104	1			T59	1		T60	1		T336	1
nak	auto[0]	endpoints[0x2]	83	1			T131	1		T138	1		T560	1
nak	auto[0]	endpoints[0x3]	80	1			T170	7		T561	1		T132	1
nak	auto[0]	endpoints[0x4]	99	1			T130	1		T288	1		T555	4
nak	auto[0]	endpoints[0x5]	83	1			T144	1		T186	16		T459	3
nak	auto[0]	endpoints[0x6]	96	1			T22	2		T76	2		T523	1
nak	auto[0]	endpoints[0x7]	95	1			T150	1		T151	1		T459	11
nak	auto[0]	endpoints[0x8]	91	1			T521	1		T121	15		T122	11
nak	auto[0]	endpoints[0x9]	83	1			T170	10		T562	1		T459	4
nak	auto[0]	endpoints[0xa]	134	1			T522	1		T563	1		T436	17
nak	auto[0]	endpoints[0xb]	130	1			T170	16		T555	3		T552	10
nak	auto[1]	endpoints[0x0]	17	1			T68	2		T564	1		T565	1
nak	auto[1]	endpoints[0x1]	9	1			T115	1		T564	1		T566	1
nak	auto[1]	endpoints[0x2]	17	1			T31	2		T567	2		T568	1
nak	auto[1]	endpoints[0x3]	10	1			T569	2		T570	1		T571	1
nak	auto[1]	endpoints[0x4]	15	1			T115	1		T568	1		T564	1
nak	auto[1]	endpoints[0x5]	10	1			T31	1		T572	1		T573	1
nak	auto[1]	endpoints[0x6]	24	1			T31	1		T115	1		T574	1
nak	auto[1]	endpoints[0x7]	23	1			T68	2		T115	1		T567	1
nak	auto[1]	endpoints[0x8]	9	1			T68	1		T115	1		T574	1
nak	auto[1]	endpoints[0x9]	16	1			T567	2		T574	1		T572	1
nak	auto[1]	endpoints[0xa]	12	1			T115	2		T567	1		T564	1
nak	auto[1]	endpoints[0xb]	19	1			T31	1		T115	1		T567	1
ack	auto[0]	endpoints[0x0]	7849	1			T30	1		T31	2		T36	1
ack	auto[0]	endpoints[0x1]	6280	1			T30	1		T31	2		T36	1
ack	auto[0]	endpoints[0x2]	3821	1			T30	1		T31	1		T36	1
ack	auto[0]	endpoints[0x3]	5382	1			T2	1		T30	1		T31	1
ack	auto[0]	endpoints[0x4]	5062	1			T30	1		T31	3		T34	1
ack	auto[0]	endpoints[0x5]	6247	1			T29	8		T30	1		T31	2
ack	auto[0]	endpoints[0x6]	3352	1			T27	1		T30	1		T31	1
ack	auto[0]	endpoints[0x7]	6857	1			T30	1		T31	2		T36	1
ack	auto[0]	endpoints[0x8]	3454	1			T30	1		T31	1		T35	1
ack	auto[0]	endpoints[0x9]	5938	1			T30	1		T31	2		T36	1
ack	auto[0]	endpoints[0xa]	5319	1			T30	1		T36	1		T4	7
ack	auto[0]	endpoints[0xb]	6290	1			T30	1		T31	3		T36	1
ack	auto[1]	endpoints[0x0]	3139	1			T30	1		T31	1		T36	1
ack	auto[1]	endpoints[0x1]	3197	1			T30	1		T31	1		T36	1
ack	auto[1]	endpoints[0x2]	3475	1			T30	1		T31	1		T36	1
ack	auto[1]	endpoints[0x3]	3305	1			T28	1		T30	1		T31	1
ack	auto[1]	endpoints[0x4]	2940	1			T30	1		T34	1		T36	1
ack	auto[1]	endpoints[0x5]	3123	1			T29	11		T30	1		T36	1
ack	auto[1]	endpoints[0x6]	2937	1			T30	1		T36	1		T37	1
ack	auto[1]	endpoints[0x7]	3373	1			T30	1		T36	1		T163	1
ack	auto[1]	endpoints[0x8]	2941	1			T30	1		T36	1		T68	1
ack	auto[1]	endpoints[0x9]	3509	1			T30	1		T31	1		T32	2
ack	auto[1]	endpoints[0xa]	3142	1			T30	1		T36	1		T4	7
ack	auto[1]	endpoints[0xb]	3307	1			T30	1		T31	1		T36	1
data1	auto[0]	endpoints[0x0]	3646	1			T5	2		T99	18		T104	2
data1	auto[0]	endpoints[0x1]	2823	1			T31	1		T57	1		T59	4
data1	auto[0]	endpoints[0x2]	1630	1			T31	1		T4	3		T57	2
data1	auto[0]	endpoints[0x3]	2408	1			T31	1		T50	1		T99	16
data1	auto[0]	endpoints[0x4]	2277	1			T31	1		T5	1		T99	15
data1	auto[0]	endpoints[0x5]	2839	1			T29	3		T4	3		T68	1
data1	auto[0]	endpoints[0x6]	1376	1			T31	1		T22	5		T4	2
data1	auto[0]	endpoints[0x7]	3132	1			T31	1		T68	1		T99	17
data1	auto[0]	endpoints[0x8]	1445	1			T6	2		T99	15		T100	12
data1	auto[0]	endpoints[0x9]	2689	1			T31	1		T4	3		T68	1
data1	auto[0]	endpoints[0xa]	2381	1			T4	1		T88	9		T68	1
data1	auto[0]	endpoints[0xb]	2837	1			T4	3		T5	1		T49	1
data1	auto[1]	endpoints[0x0]	1716	1			T68	2		T5	3		T99	15
data1	auto[1]	endpoints[0x1]	1780	1			T31	2		T57	1		T99	21
data1	auto[1]	endpoints[0x2]	1952	1			T31	1		T4	4		T57	2
data1	auto[1]	endpoints[0x3]	1788	1			T31	1		T50	1		T99	12
data1	auto[1]	endpoints[0x4]	1584	1			T68	1		T5	3		T99	20
data1	auto[1]	endpoints[0x5]	1715	1			T29	3		T4	3		T5	3
data1	auto[1]	endpoints[0x6]	1614	1			T31	1		T4	5		T5	2
data1	auto[1]	endpoints[0x7]	1886	1			T99	18		T100	7		T164	6
data1	auto[1]	endpoints[0x8]	1609	1			T31	1		T68	2		T6	4
data1	auto[1]	endpoints[0x9]	1923	1			T31	1		T32	2		T4	3
data1	auto[1]	endpoints[0xa]	1753	1			T4	6		T68	1		T5	2
data1	auto[1]	endpoints[0xb]	1826	1			T31	1		T4	3		T5	4
data0	auto[0]	endpoints[0x0]	4568	1			T30	1		T31	2		T36	1
data0	auto[0]	endpoints[0x1]	3793	1			T30	1		T31	1		T36	1
data0	auto[0]	endpoints[0x2]	2547	1			T30	1		T36	1		T4	4
data0	auto[0]	endpoints[0x3]	3343	1			T2	1		T30	1		T36	1
data0	auto[0]	endpoints[0x4]	3185	1			T30	1		T31	2		T34	1
data0	auto[0]	endpoints[0x5]	3715	1			T29	5		T30	1		T31	2
data0	auto[0]	endpoints[0x6]	2402	1			T27	1		T30	1		T33	1
data0	auto[0]	endpoints[0x7]	4091	1			T30	1		T31	1		T36	1
data0	auto[0]	endpoints[0x8]	2363	1			T30	1		T31	1		T35	1
data0	auto[0]	endpoints[0x9]	3526	1			T30	1		T31	1		T36	1
data0	auto[0]	endpoints[0xa]	3404	1			T30	1		T36	1		T4	6
data0	auto[0]	endpoints[0xb]	3860	1			T30	1		T31	3		T36	1
data0	auto[1]	endpoints[0x0]	1491	1			T30	1		T31	2		T36	1
data0	auto[1]	endpoints[0x1]	1518	1			T30	1		T31	1		T36	1
data0	auto[1]	endpoints[0x2]	1614	1			T30	1		T31	3		T36	1
data0	auto[1]	endpoints[0x3]	1580	1			T28	1		T30	1		T31	1
data0	auto[1]	endpoints[0x4]	1446	1			T30	1		T31	2		T34	1
data0	auto[1]	endpoints[0x5]	1469	1			T29	8		T30	1		T31	1
data0	auto[1]	endpoints[0x6]	1408	1			T30	1		T36	1		T37	1
data0	auto[1]	endpoints[0x7]	1595	1			T30	1		T36	1		T163	1
data0	auto[1]	endpoints[0x8]	1395	1			T30	1		T36	1		T6	3
data0	auto[1]	endpoints[0x9]	1650	1			T30	1		T32	1		T36	1
data0	auto[1]	endpoints[0xa]	1436	1			T30	1		T36	1		T4	1
data0	auto[1]	endpoints[0xb]	1585	1			T30	1		T31	2		T36	1