Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8202

1

T42

1

T43

2

T6

6

auto[1]

54285

1

T28

1

T42

2

T29

11

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55135

1

T28

1

T42

1

T29

11

auto[1]

7352

1

T42

2

T6

30

T103

1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55970

1

T28

1

T42

3

T29

11

auto[1]

6517

1

T105

1

T117

3

T106

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4637

1

T43

3

T6

8

T117

1

pkt_types[PidTypeInToken]

57850

1

T28

1

T42

3

T29

11

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1366

1

T43

1

T6

1

T117

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

717

1

T398

1

T121

14

T413

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

83

1

T6

5

T104

2

T381

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

13

1

T400

1

T463

1

T477

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1442

1

T43

2

T6

1

T398

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

892

1

T118

1

T121

20

T122

29

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

110

1

T6

1

T104

4

T381

3

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

14

1

T575

1

T474

1

T403

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3812

1

T42

1

T43

1

T380

5

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2108

1

T117

1

T398

2

T121

69

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

51

1

T576

1

T443

1

T450

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

52

1

T117

2

T449

1

T401

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

42123

1

T28

1

T29

11

T43

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2675

1

T105

1

T106

1

T118

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

6983

1

T42

2

T6

24

T103

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

46

1

T400

2

T525

1

T401

3